參數(shù)資料
型號： LMX2470
廠商： National Semiconductor Corporation
英文描述： 2.6 GHz Delta-Sigma Fractional-N PLL with 800 MHz Integer-N PLL
中文描述： 2.6 GHz的Δ-Σ分?jǐn)?shù)N與800兆赫整數(shù)N分頻PLL鎖相環(huán)
文件頁數(shù)： 33/36頁
文件大?。?/td> 453K
代理商： LMX2470
Programming Description
(Continued)
2.7.5 FM[1:0] -- Fractional Mode
Determines the order of the delta-sigma modulator. Higher order delta-sigma modulators reduce the spur levels closer to the
carrier by pushing this noise to higher frequency offsets from the carrier. In general, the order of the loop filter should be at least
one greater than the order of the delta-sigma modulator in order to allow for sufficient roll-off.
FM
0
1
2
3
Function
Fractional PLL mode with a 4th order delta-sigma modulator
Disable the delta-sigma modulator. Recommended for test use only.
Fractional PLL mode with a 2nd order delta-sigma modulator
Fractional PLL mode with a 3rd order delta-sigma modulator
2.7.6 FDM -- Fractional Denominator Mode
When this bit is set to 0, the part operates with a 12- bit fractional denominator. For most applications, 12-bit mode should be
adequate, but for those applications requiring ultra fine tuning resolution, there is 22-bit mode. Note that the PLL may consume
slightly more current when it is in 22-bit mode.
FDM
0
1
Bits for Fractional Denominator/Numerator
12-bit
22-bit
Maximum Size of Fractional Denominator/Numerator
4095
4194303
2.7.7 IF_CPP -- IF PLL Charge Pump Polarity
When this bit is set to 1, the phase detector polarity for the IF PLL charge pump is positive. Otherwise set this bit to 0 for a
negative phase detector polarity
2.7.8 IF_CPT -- IF PLL Charge Pump TRI-STATE Mode
This bit enables the user to put the charge pump in a TRI-STATE ( high impedance ) condition. Note that if there is a conflict, the
ATPU bit overrides this bit.
RF_CPT
0
1
Charge Pump State
ACTIVE
TRI-STATE
2.7.9 RF_CPP -- RF PLL Charge Pump Polarity
For a positive phase detector polarity, which is normally the case, set this bit to 1. Otherwise set this bit to 0 for a negative phase
detector polarity.
2.7.10 RF_CPT -- RF PLL Charge Pump TRI-STATE Mode
This bit enables the user to put the charge pump in a TRI-STATE ( high impedance) condition. Note that if there is a conflict, the
ATPU bit overrides this bit.
RF_CPT
0
1
Charge Pump State
Active
TRI-STATE
L
www.national.com
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相關(guān)PDF資料
PDF描述
LMX2470SLEX 2.6 GHz Delta-Sigma Fractional-N PLL with 800 MHz Integer-N PLL
LMX2485 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL
LMX2485E 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL
LMX2485ESQ 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL
LMX2485ESQX 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LMX2470EVAL 功能描述:時鐘和定時器開發(fā)工具 LMX2470 EVAL BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
LMX2470SLEX 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
LMX2470SLEX/NOPB 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
LMX2471 制造商:NSC 制造商全稱:National Semiconductor 功能描述:3.6 GHz Delta-Sigma Fractional-N PLL with 1.7 GHz Integer-N PLL
LMX2471 WAF 制造商:Texas Instruments 功能描述:
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