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參數(shù)資料
| 型號： | LMX2470 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 2.6 GHz Delta-Sigma Fractional-N PLL with 800 MHz Integer-N PLL |
| 中文描述： | 2.6 GHz的Δ-Σ分數(shù)N與800兆赫整數(shù)N分頻PLL鎖相環(huán) |
| 文件頁數(shù)： | 24/36頁 |
| 文件大小： | 453K |
| 代理商： | LMX2470 |
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Programming Description
2.0 GENERAL PROGRAMMING INFORMATION
The descriptions below describe the 24-bit data registers loaded through the MICROWIRE Interface. These data registers are
used to program the R counter, the N counter, and the internal mode control latches. The data format of a typical 24-bit data
register is shown below. The control bits CTL [3:0] decode the register address. On the rising edge of LE, data stored in the shift
register is loaded into one of the appropriate latches (selected by address bits). Data is shifted in MSB first. Note that it is best
to program the N counter last, since doing so initializes the digital lock detector and Fastlock circuitry. Note that initialize means
it resets the counters, but it does NOT program values into these registers. Upon a cold power-up, it is necessary to program all
the registers. The exception is when 22-bit is not being used. In this case, it is not necessary to program the R7 register.
MSB
LSB
DATA [21:0]
CTL [3:0]
23
4
3
2
1
0
2.0.1 Register Location Truth Table
The control bits CTL [2:0] decode the internal register address. The table below shows how the control bits are mapped to the
target control register.
C3
x
0
0
0
0
1
1
1
1
C2
x
0
0
1
1
0
0
1
1
C1
x
0
1
0
1
0
1
0
1
C0
0
1
1
1
1
1
1
1
1
DATA Location
R0
R1
R2
R3
R4
R5
R6
R7
R8
2.0.2 Control Register Content Map
Because the LMX2470 registers are complicated, they are organized into two groups, basic and advanced. The first four registers
are basic registers that contain critical information necessary for the PLL to achieve lock. The last 5 registers are for features that
optimize spur, phase noise, and lock time performance. The next page shows these registers.
L
www.national.com
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相關PDF資料 |
PDF描述 |
|---|---|
| LMX2470SLEX | 2.6 GHz Delta-Sigma Fractional-N PLL with 800 MHz Integer-N PLL |
| LMX2485 | 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL |
| LMX2485E | 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL |
| LMX2485ESQ | 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL |
| LMX2485ESQX | 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2470EVAL | 功能描述:時鐘和定時器開發(fā)工具 LMX2470 EVAL BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| LMX2470SLEX | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2470SLEX/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2471 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:3.6 GHz Delta-Sigma Fractional-N PLL with 1.7 GHz Integer-N PLL |
| LMX2471 WAF | 制造商:Texas Instruments 功能描述: |
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