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參數(shù)資料
| 型號： | LMX2470 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 2.6 GHz Delta-Sigma Fractional-N PLL with 800 MHz Integer-N PLL |
| 中文描述： | 2.6 GHz的Δ-Σ分?jǐn)?shù)N與800兆赫整數(shù)N分頻PLL鎖相環(huán) |
| 文件頁數(shù)： | 21/36頁 |
| 文件大?。?/td> | 453K |
| 代理商： | LMX2470 |
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Functional Description
(Continued)
1.6.1 Determining the Loop Gain Multiplier, K
The loop bandwidth multiplier, K, is needed in order to de-
termine the theoretical impact of fastlock/CSR on the loop
bandwidth and also which resistor should be switched in
parallel with the loop filter resistor R2. K = K_K · K_Fcomp
where K is the loop gain multiplier K_K is the ratio of the
Fastlock charge pump current to the steady state charge
pump current. Note that this should always be greater than
or equal to one. K_Fcomp is the ratio of the Fastlock com-
parison frequency to the steady state comparison frequency.
If this ratio is less than one, this implies that the CSR is being
used.
1.6.2 Determining the Theoretical Lock Time
Improvement and Fastlock Resistor, R2’
When using fastlock, it is necessary to switch in a resistor
R2’, in parallel with R2 in order to keep the loop filter opti-
mized and maintain the same phase margin. After the PLL
has achieved a frequency that is sufficiently close to the
desired frequency, the resistor R2’ is disengaged and the
charge pump current is and comparison frequency are re-
turned to normal. Of special concern is the glitch that is
caused when the resistor R2’ is disengaged. This glitch can
take up a significant portion of the lock time. The LMX2470
has enhanced switching circuitry to minimize this glitch and
therefore improve the lock time.
20059340
The change in loop bandwidth is dependent upon the loop
gain multiplier, K, as determined in section 4. The theoretical
improvement in lock time is given below, but the actual
improvement will be less than this due to the glitch that is
caused by disengaging Fastlock. The theoretical improve-
ment is given to show an upper bound on what improvement
is possible with Fastlock. In the case that K
<
1, this implies
the CSR is being engaged and that the theoretical lock time
will be degraded. However, since this mode reduces or
eliminates cycle slipping, the actual lock time may be better
in cases where the loop bandwidth is small relative to the
comparison frequency. Realize that the theoretical lock time
multiplier does not account for the fastlock/CSR disengage-
ment glitch, which is most severe for larger values of K.
Loop Gain
Multiplier, K
1:8
*
1:4
*
1:2
*
4:1
8:1
16:1
32:1
Loop Bandwidth
Multiplier
0.35
0.50
0.71
2.00
2.83
4.00
5.66
R2’ Value
Lock Time
Multiplier
x 2.828
x 2.000
x 1.414
x 0.500
x 0.354
x 0.250
x 0.177
open
open
open
R2/1.00
R2/1.83
R2/3.00
R2/4.65
* These modes of operation are generally not recommended
1.6.3 Using Fastlock and Cycle Slip Reduction (CSR)
to Avoid Cycle Slipping
In the case that the comparison frequency is very large ( i.e.
100 X ) of the loop bandwidth, cycle slipping may occur when
an instantaneous phase error is presented to the phase
detector. This can be reduced by increasing the loop band-
width during frequency acquisition, decreasing the compari-
son frequency during frequency acquisition, or some combi-
nation of the these. If increasing the loop bandwidth during
frequency acquisition is not sufficient to reduce cycle slip-
ping, the LMX2470 also has a routine to decrease the com-
parison frequency.
L
www.national.com
21
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LMX2470SLEX | 2.6 GHz Delta-Sigma Fractional-N PLL with 800 MHz Integer-N PLL |
| LMX2485 | 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL |
| LMX2485E | 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL |
| LMX2485ESQ | 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL |
| LMX2485ESQX | 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2470EVAL | 功能描述:時鐘和定時器開發(fā)工具 LMX2470 EVAL BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| LMX2470SLEX | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2470SLEX/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2471 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:3.6 GHz Delta-Sigma Fractional-N PLL with 1.7 GHz Integer-N PLL |
| LMX2471 WAF | 制造商:Texas Instruments 功能描述: |
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