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參數(shù)資料
| 型號： | LM9627CCEA |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | BZ Series Standard Basic Switch, Single Pole Double Throw Circuitry, 15 A at 125 Vac, Overtravel Plunger Actuator, 2,5 N - 3,61 N [9 oz - 13 oz] Operating Force, Silver Contacts, Screw Termination, CE, CSA, DEMKO, |
| 中文描述： | 彩色CMOS圖像傳感器顯卡30醫(yī)科 |
| 文件頁數(shù)： | 23/37頁 |
| 文件大小： | 370K |
| 代理商： | LM9627CCEA |
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Functional Description
(continued)
14.6
The sensor’s digital video port’s synchronisation signals can be
programmed to operate in slave mode. In slave mode the inte-
grated timing and control block will only start frame and row pro-
cessing upon the receipt of triggers from an external source.
Synchronisation Signals in Slave Mode
Only two synchronization signals are used in slave mode as fol-
lows:
hsync
is the row trigger input signal.
vsync
is the frame trigger input signal.
Figure 46 shows the LM9627’s digital video port in slave mode
connected to a digital video processor master DVP.
Figure 46. LM9627 in slave mode
14.7
The row trigger input pin,
hsync
, is used to trigger the process-
ing of a given row. It must be activated for at least two “
mclk
”
cycle. The first pixel data will appear at
d[11:0]
“X
mclk
“periods
after the assertion of the row trigger, were
X
mclk
is given by:
Row Trigger Input Pin (hsync)
Where:
DW
StAd
is the value of the display window column start
address.
The polarity of the active level of the row trigger is programma-
ble. By default it is active high.
14.8
The frame trigger input pin,
vsync
, is used to reset the row
address counter and prepare the array for row processing. It
must be activated for at least one “
mclk
” cycle and no more than
96 mclk cycles after the activation of
hsync
as illustrated in Fig-
ure 48.
Frame Trigger Input Pin (vsync)
The polarity of the active level of the row trigger is programma-
ble. By default it is active high.
RowTrig
FrameTrig
MasterClock
din[11:0]
d[11:0]
hsync
vsync
pclk
mclk
DVP
LM9627
X
mclk
= 124 + DW
StAd
Figure 47. hsync slave mode timing diagram for centred display window of 642 pixels
Figure 48. vsync slave mode timing diagram for scan window of 504 rows.
779
778
777
776
0
1
3
2
134 135 136 136 137
779
778
777
0
1
776
775
774
...
...
hsync
pixel 11
pixel 12
pixel 652
d[11:0]
mclk
mclk
count
642 valid pixels
780 clock cycles per line
779
778
777
776
0
1
3
2
779
778
777
0
1
776
775
774
...
hsync
mclk
mclk
count
780 clock cycles per line
internal row
counter
line502
line 502
No more than
96 clock cycles
vsync
...
779
778
777
0
1
776
775
774
line503
line 0
L
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| LM9628SAMPLE-KIT | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LM9628 Color CMOS Image Sensor VGA 30 FPS |
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