參數(shù)資料
型號: LM9627CCEA
廠商: National Semiconductor Corporation
英文描述: BZ Series Standard Basic Switch, Single Pole Double Throw Circuitry, 15 A at 125 Vac, Overtravel Plunger Actuator, 2,5 N - 3,61 N [9 oz - 13 oz] Operating Force, Silver Contacts, Screw Termination, CE, CSA, DEMKO,
中文描述: 彩色CMOS圖像傳感器顯卡30醫(yī)科
文件頁數(shù): 15/37頁
文件大?。?/td> 370K
代理商: LM9627CCEA
Confidential
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www.national.com
Functional Description
(continued)
6.0
The LM9627 contains a clock generation module that will create
two clocks as follows:
Hclk,
the horizontal clock. This is an internal system
clock and can be programmed to be the input
clock
(mclk)
or
mclk
divided
by any number
between 1 and 255.
CLK
pixel
the pixel clock. This is the external pixel clock
that appears at the digital video port. It can be
Hclk
or
Hclk
divided by 2. This clock cannot be
programed.
CLOCK GENERATION MODULE
7.0
A frame is defined as the time it takes to reset every pixel in the
array, integrate the incident light, convert it to digital data and
present it on the digital video port. This is not a concurrent pro-
cess and is characterized in a series of events each needing a
certain amount of time as shown in Figure 23.
FRAME RATE PROGRAMING
Figure 23. Frame Readout Flow Diagram
7.1
Full frame integration is when each pixel in the array integrates
light incident on it for the duration of a frame (see Figure 24).
Full Frame Integration
The number of
Hclk
clock cycles required to process & shift out
one row of pixels is given by:
Where:
R
opcycle
is a fixed integer value of 780 representing the
Row Operation Cycle Time
in multiples
of
Hclk
clock cycles. It is the time required to carry out
all fixed row operations outlined in Figure 23.
a programmable value between 0 & 2047 repre-
senting the
Row Delay Time
in multiples of
Hclk
.
This parameter allows the
Row Operation Cycle
time to be extended. (See the Row Delay High
and Row Delay Low registers).
R
delay
The number of rows in a scan window is given by:
Where:
RAD
end
is the end row address of the defined scan win-
dow. (See section 2.1)
is the start row address of the defined scan win-
dow. (Scan section 2.1).
RAD
start
The number of
Hclk
clocks required to process a full frame is
given by:
Where:
M
factor
is a Mode Factor which must be applied. It is
dependent on the selected mode of operation as
shown in the table below:
SWN
rows
is the
Number of Rows in Selected Scan Win-
dow
.
F
delay
a programmable value between 0 & 4097 repre-
senting the
Inter Frame Delay
in multiples of
RN
Hclk
. This parameter allows the frame time to
be extended. (See the Frame Delay High and
Frame Delay Low registers).
The frame rate is given by:
7.2
In some cases it is desirable to reduce the time during which the
pixels in the array are allowed to integrate incident light without
changing the frame rate.
Partial Frame Integration
This is known as
Partial Fame Integration
and can be achieved
by resetting pixels in a given row ahead of the row being
selected for readout as shown in Figure 24. The number of
Hclk
clocks required to process a partial frame is given by:
Where:
RN
Hclk
is the number of
Hclk
clock cycles required to
process & shift out one row of pixels.
is the number of rows ahead of the current row
to be reset. (See the Integration Time High and
Low registers).
The Integration time is subject to the following limits:
I
time
Start
Row address = 0
Row delay time
Transfer all pixels to CDS
Shift all pixels out of row
Row address + 1
Last row
Reset all pixels in row
Yes
No
R
RN
Hclk
= R
opcycle
+ R
delay
Progressive Scan
1
Sub-sampling or Interlace
0.5
Mode
Limit
Progressive Scan
I
time
<=
SWN
rows +
F
delay
Interlace
I
time
<=
SWN
rows +
2
*
F
delay
Sub-Sampled
I
time
<=
SWN
rows +
0.5
*
F
delay
SWN
rows
= (RAD
end
- RAD
start
) + 1
FN
Hclk
= [(M
factor
*
SWN
rows
)
+ F
delay
]
*
RN
Hclk
Hclk
FN
Hclk
Frame Rate =
FP
Hclk
= RN
Hclk *
I
time
L
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