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參數(shù)資料
| 型號(hào)： | LM9627CCEA |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | BZ Series Standard Basic Switch, Single Pole Double Throw Circuitry, 15 A at 125 Vac, Overtravel Plunger Actuator, 2,5 N - 3,61 N [9 oz - 13 oz] Operating Force, Silver Contacts, Screw Termination, CE, CSA, DEMKO, |
| 中文描述： | 彩色CMOS圖像傳感器顯卡30醫(yī)科 |
| 文件頁(yè)數(shù)： | 14/37頁(yè) |
| 文件大?。?/td> | 370K |
| 代理商： | LM9627CCEA |
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Functional Description
(continued)
Figure 19. Snapshot Trigger Generation Logic
Figure 20. Auto Snapshot Mode State Diagram
5.4
In CPU snapshot mode, the
FTriggerEN
is not set automatically
and an Interrupt generator can be enabled.
CPU Snapshot Mode
Hence, upon the receipt of a
snapshot
or
FTriggerNow
trigger
signal, the integrated timing and control circuit will generate an
internal TRIGGER signal as shown in figure 19 and then wait in
the IRQ state for the
FTriggerEN
bit to be manually set as shown
in figure 21.
Once the
FtriggerEn
bit is set the integrated timing and control
circuit will start resetting the array one row at a time. At end of
the reset cycle the timing and control circuit will signal the shut-
ter to open via
extsync
pin or
FtSync
bit. At the end of the pro-
grammed integration time the shutter will be signalled to close,
and the pixel read-out will commence as shown in figure 18a. At
the end of the read-out sequence the
FTriggerEN
will be auto-
matically disabled and the sensor will return to video capture
mode as shown in figure 20.
If an external shutter is not available then at least two frames
need to be taken so that the pixels can be integrated over one
frame as shown in Figure 18b.
To use CPU snapshot mode the
SsEngage
bit of the
SNAPSHOTMODE1 register must be set to one.
An interrupt generator can be enabled in CPU snapshot mode
by setting the
SnapIntEn
bit of SNAPSHOTMODE1 register. An
interrupt will be generated on the external interrupt pin,
irq
,
when a snapshot sequence is triggered (TRIGGER=1) or when
the array readout is complete at the end of the snapshot
sequence as shown figure 21.
Figure 21. CPU Snapshot Mode State Diagram
When an interrupt is generated by a TRIGGER event, the
SsTrigFlag
bit in the SNAPSHOTMODE1 register is set. Simi-
larly when an interrupt is generated at the completion of a read-
out the
SsRdFlag
in the SNAPSHOTMODE1 register is set.
The polarity of the
irq
pin can be programmed. The interrupt can
only be cleared by reading
SsTrigFlag
and the
SsRdFlag
as
shown in figure 22.
Figure 22. Interrupt Request Generation Logic
5.5
The
snapshot
pin can be programmed to operate in
pulse trig-
ger mode
where one snapshot sequence is executed per active
pulse or in
level trigger mode
where by snapshot sequences are
repeated as long as the level on the
snapshot
pin is held active.
(see figures 20 and 21).
Pulse & Level Trigger Mode
Pulse and level trigger modes can be set by programming the
SnapshotMod
bit in the SNAPSHOTMODE0 register.
snapshot
SnapShotPol
SnapEnable
FTriggerNow
TRIGGER
VIDEO
SNAP
PREVIEW
c:TRIGGER==1
c
S
S
a:FTriggerEn=1
a:FTriggerEn=0
VIDEO
IRQ
a:
SsTrigFlag
=1
SNAP
c:FTriggerEn==1
PREVIEW
a: SsRdFlag = 1
a: FtTriggerEn = 0
c:TRIGGER==1
c
(
S
S
SsTrigFlag
SsRdFlag
SnapIntEn
IrqPol
irq
L
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