參數(shù)資料
型號: LM9627CCEA
廠商: National Semiconductor Corporation
英文描述: BZ Series Standard Basic Switch, Single Pole Double Throw Circuitry, 15 A at 125 Vac, Overtravel Plunger Actuator, 2,5 N - 3,61 N [9 oz - 13 oz] Operating Force, Silver Contacts, Screw Termination, CE, CSA, DEMKO,
中文描述: 彩色CMOS圖像傳感器顯卡30醫(yī)科
文件頁數(shù): 13/37頁
文件大?。?/td> 370K
代理商: LM9627CCEA
Confidential
13
www.national.com
Functional Description
(continued)
5.0
The LM9627 is capable of capturing a single frame of an image
under hardware or software control, with or without the aid of an
external
shutter.
Two
registers,
SNAPSHOTMODE1, are provided to program, monitor and con-
trol all snapshot sequences.
SNAPSHOT MODE
SNAPSHOTMODE0
&
5.1
The snapshot mode events can be software controlled by writing
to and reading from the snapshot mode registers over the I
2
C
compatible interface.
Software Controlled Snapshots
5.2
Two dedicated pins are provided on the LM9627,
snapshot
&
extsync
,
allowing the snapshot mode events to be controlled by
hardware
.
The
snapshot
pin must be enabled by writing to the
SnapEnable
bit of the MCFG0 register.
Hardware Controlled Snapshots
5.3
In auto snapshot mode (see figure 20), upon the receipt of a
snapshot
or
FTriggerNow
trigger signal, the integrated timing and
control circuit will set the
FTriggerEN
bit and generate an inter-
nal TRIGGER signal (see figure 19), thus resetting the array one
row at a time. At end of the reset cycle the timing and control cir-
cuit will signal the shutter to open via
extsync
pin or
FtSync
bit.
At the end of the programmed integration time the shutter will be
signalled to close, and the pixel read-out will commence as
shown in figure 18a. At the end of the read-out sequence the
FTriggerEN
will be automatically reset and the sensor will return
to video capture mode as shown in figure 20.
Auto Snapshot Mode
If an external shutter is not available then at least two frames
need to be taken so that the pixels can be integrated over one
frame as shown in Figure 18b.
To use auto snapshot mode the
SsEngage
bit of the
SNAPSHOTMODE1 register must be set to zero.
Note 1:
Note 2:
Note 3:
This wave form shows the
snapshot
pin programmed to the default pulse mode.
The
irq
pulse is taken low when the snapshot trigger interrupt flag (
SsTrigFlag
) in the snapshot mode1 (
SNAPMODE1
) register is read.
The
irq
pulse is taken low when the snapshot trigger interrupt flag (
SsRdFlag
) in the snapshot mode1 (
SNAPMODE1
) register is read.
Figure 18. Snapshot Mode
Start Snapshot Sequence
Start of Array Reset Frames
Open Shutter
Close shutter & start read-out
Read-out complete
FTriggerEn
snapshot
or
FTriggerNow
extsync
or
FtSync
FtBusy
Array reset,
irq
programmable 1 to 4 frames
Capture
image
Data
read-out
note 1
note 2
note 3
Start Snapshot sequence
Start of Array Reset Frames
Integration Start
Start Read-out
Read-out Complete
FTriggerEn
snapshot
or
FTriggerNow
extsync
or
FtSync
FtBusy
Bold
external pins
italic
register bits
Array reset,
irq
programmable 1 to 4 frames
Capture
image
Data
read-out
note 1
note 2
note 3
a) With External Shutter
b) Without External Shutter
L
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