參數(shù)資料
型號(hào)： LM93CIMT
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 電源管理
英文描述： Hardware Monitor with Integrated Fan Control for Server Management
中文描述： 16-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO56
封裝： MO-153EE, TSSOP-56
文件頁(yè)數(shù)： 82/92頁(yè)
文件大小： 654K
代理商： LM93CIMT
16.0 Registers
(Continued)
16.9.4 Register E7h
S3 GPI Mask
Register
Address
Read/
Write
Register
Name
S3 GPI
Mask
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
Value
E7h
R/W
GPI7_S3
_MSK
GPI6_S3
_MSK
GPI5_S3
_MSK
GPI4_S3
_MSK
GPI3_S3
_MSK
GPI2_S3
_MSK
GPI1_S3
_MSK
GPI0_S3
_MSK
FFh
Bit
0
1
2
3
4
5
6
7
Name
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
GPI0_S3_MSK
GPI1_S3_MSK
GPI2_S3_MSK
GPI3_S3_MSK
GPI4_S3_MSK
GPI5_S3_MSK
GPI6_S3_MSK
GPI7_S3_MSK
If set, GPI0 errors are masked in S3 sleep state.
If set, GPI1 errors are masked in S3 sleep state.
If set, GPI2 errors are masked in S3 sleep state.
If set, GPI3 errors are masked in S3 sleep state.
If set, GPI4 errors are masked in S3 sleep state.
If set, GPI5 errors are masked in S3 sleep state.
If set, GPI6 errors are masked in S3 sleep state.
If set, GPI7 errors are masked in S3 sleep state.
16.9.5 Register E8h
S3 Tach Mask
Register
Address
Read/
Write
Register
Name
S3 Tach
Mask
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
Value
E8h
R/W
RES
TACH4_S3
_MSK
TACH3_S3
_MSK
TACH2_S3
_MSK
TACH1_S3
_MSK
0Fh
Bit
0
1
2
3
7:4
Name
R/W
R/W
R/W
R/W
R/W
R
Description
TACH1_S3_MSK
TACH2_S3_MSK
TACH3_S3_MSK
TACH4_S3_MSK
RES
If set, Tach1 errors are masked in S3 sleep state.
If set, Tach2 errors are masked in S3 sleep state.
If set, Tach3 errors are masked in S3 sleep state.
If set, Tach4 errors are masked in S3 sleep state.
Reserved
16.9.6 Register E9h
S3 Temperature/Voltage Mask
Register
Address
Read/
Write
Register
Name
S3 Voltage
Mask
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
Value
E9h
R/W
RES
TEMP_
S3_MSK
AIN14_S3
_MSK
AIN13_S3
_MSK
AIN12_S3
_MSK
07h
Bit
0
1
2
3
Name
R/W
R/W
R/W
R/W
R/W
Description
AIN12_S3_MSK
AIN13_S3_MSK
AIN14_S3_MSK
TEMP_S3_MSK
If set, AIN12 errors as masked in S3 sleep state.
If set, AIN13 errors as masked in S3 sleep state.
If set, AIN14 errors as masked in S3 sleep state.
If set, temperature errors and diode fault errors for
zones 1 and 2 are masked in S3 sleep state.
Reserved
7:3
RES
R
L
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