參數(shù)資料
型號(hào)： LM93CIMT
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類(lèi)： 電源管理
英文描述： Hardware Monitor with Integrated Fan Control for Server Management
中文描述： 16-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO56
封裝： MO-153EE, TSSOP-56
文件頁(yè)數(shù)： 74/92頁(yè)
文件大?。?/td> 654K
代理商： LM93CIMT
16.0 Registers
(Continued)
16.8.18 Register CDh
PWM2 Control 2
Register
Address
Read/
Write
Register
Name
PWM2
Control 2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
Value
CDh
R/W
OVR_DC
PL
EPPL
INV
OVR
00h
Bit
0
Name
OVR
R/W
R/W
Description
When set, enables manual duty cycle override for
PWM2.
Invert PWM1 output. When 0, 100% duty cycle
corresponds to the PWM output continuously HIGH.
When 1, 100% duty cycle corresponds to the PWM
output continuously LOW.
Enable PROCHOT PWM2 lock. When set, this bit
causes bound PROCHOT events on PWM2 to trigger
PPL (bit [3]). When cleared, PPL never gets set.
PROCHOT PWM2 lock. When set, this bit indicates
that PWM2 is currently being held at 100% because a
bound PROCHOT event occurred while EPPL (bit [2])
was set. This bit is cleared by writing a zero. Clearing
this bit allows the fans to return to normal operation.
This bit is not locked by the LOCK bit in the LM93
Configuration register.
This field sets the duty cycle that will be used by
PWM2 whenever manual override mode is active.
This field accepts 16 possible values that are mapped
to duty cycles according the table in the Fan Control
section. Whenever this register is read, it returns the
duty cycle that is currently being used by PWM2
regardless of whether override mode is active or not.
The value read may not match the last value written if
another control source is requesting a greater duty
cycle. This field always returns 0h when the PWM2
spin up cycle is active.
1
INV
R/W
2
EPPL
R/W
3
PPL
R/W
7:4
OVR_DC
R/W
L
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