參數(shù)資料
型號: LM93CIMT
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 電源管理
英文描述: Hardware Monitor with Integrated Fan Control for Server Management
中文描述: 16-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO56
封裝: MO-153EE, TSSOP-56
文件頁數(shù): 44/92頁
文件大?。?/td> 654K
代理商: LM93CIMT
16.0 Registers
(Continued)
16.4.6 Register 45h
B_P2_PROCHOT Error Status
Register
Address
Read/
Write
Register
Name
B_P2_PROCHOT
Error Status
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
Value
45h
RWC
PH2
_ERR
TMAX
T100
T75
T50
T25
T12
T0
00h
Bit
Name
R/W
Description
Sleep
Masking
S3, S4/5
0
T0
RWC Set when P2_PROCHOT has had a throttled event. This bit is set for any
amount of PROCHOT throttling
>
0%.
RWC Set when P2_PROCHOT has throttled greater than or equal to 0.0% but less
than 12.5%.
RWC Set when P2_PROCHOT has throttled greater than or equal to 12.5% but
less than 25%.
RWC Set when P2_PROCHOT has throttled greater than or equal to 25% but less
than 50%.
RWC Set when P2_PROCHOT has throttled greater than or equal to 50% but less
than 75%.
RWC Set when P2_PROCHOT has throttled greater than or equal to 75% but less
than 100%.
RWC Set when P2_PROCHOT has throttled 100%.
RWC Set when P2_PROCHOT has throttled more than the user limit.
1
T12
S3, S4/5
2
T25
S3, S4/5
3
T50
S3, S4/5
4
T75
S3, S4/5
5
T100
S3, S4/5
6
7
TMAX
PH2_ERR
S3, S4/5
S3, S4/5
The PH2_ERR bit is the only bit in this register that will set BMC_ ERR in the LM93 Status/Control register.
16.4.7 Register 46h
B_GPI Error Status
Register
Address
Read/
Write
Register
Name
B_GPI
Error Status
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
Value
46h
RWC
GPI7
_ERR
GPI6
_ERR
GPI5
_ERR
GPI4
_ERR
GPI3
_ERR
GPI2
_ERR
GPI1
_ERR
GPI0
_ERR
00h
Bit
Name
R/W
Description
Sleep
Masking
S1*, S3*, S4/5*
0
GPI0_ERR
RWC This bit is set whenever GPIO0 is driven low (unless masked via the GPI
Error Mask register).
RWC This bit is set whenever GPIO1 is driven low (unless masked via the GPI
Error Mask register).
RWC This bit is set whenever GPIO2 is driven low (unless masked via the GPI
Error Mask register).
RWC This bit is set whenever GPIO3 is driven low (unless masked via the GPI
Error Mask register).
RWC This bit is set whenever GPIO4 is driven low (unless masked via the GPI
Error Mask register).
RWC This bit is set whenever GPIO5 is driven low (unless masked via the GPI
Error Mask register).
RWC This bit is set whenever GPIO6 is driven low (unless masked via the GPI
Error Mask register).
RWC This bit is set whenever GPIO7 is driven low (unless masked via the GPI
Error Mask register).
1
GPI1_ERR
S1*, S3*, S4/5*
2
GPI2_ERR
S1*, S3*, S4/5*
3
GPI3_ERR
S1*, S3*, S4/5*
4
GPI4_ERR
S1*, S3*, S4/5*
5
GPI5_ERR
S1*, S3*, S4/5*
6
GPI6_ERR
S1*, S3*, S4/5*
7
GPI7_ERR
S1*, S3*, S4/5*
L
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