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參數(shù)資料
| 型號： | LLT3837EFE |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING CONTROLLER, 110 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, TSSOP-16 |
| 文件頁數(shù)： | 8/28頁 |
| 文件大?。?/td> | 255K |
| 代理商： | LLT3837EFE |
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LT3837
16
3837fa
APPLICATIONS INFORMATION
Optimization might show that a more efcient solution
is obtained at higher peak current but lower inductance
and the associated winding series resistance. A simple
spreadsheet program is useful for looking at tradeoffs.
Transformer Core Selection
Once LP is known, the type of transformer is selected.
High efciency converters use ferrite cores to minimize
core loss. Actual core loss is independent of core size for
a xed inductance, but decreases as inductance increases.
Since increased inductance is accomplished through
more turns of wire, copper losses increase. Thus trans-
former design balances core and copper losses. Remem-
ber that increased winding resistance will degrade cross
regulation and increase the amount of load compensa-
tion required.
The main design goals for core selection are reducing
copper losses and preventing saturation. Ferrite core mate-
rial saturates hard, rapidly reducing inductance when the
peak design current is exceeded. This results in an abrupt
increase in inductor ripple current and, consequently, out-
put voltage ripple. Do not allow the core to saturate! The
maximum peak primary current occurs at minimum VIN:
I
P
VDC
X
now
DC
PK
IN
IN MIN
MAX
MIN
MA
=+
()
:
1
2
X
IN MIN
OUT
MIN
NV
V
X
V
=
+
=
+
=
1
3
9
33
52 4
.
.%
()
IIN MIN
MAX
OSC
P
IN
DC
fL
P
kH
()
.
()
=
()
2
90 52
200
zzH
W
.
.
7 8
37 5
0 380
μ
=
Using the example numbers leads to:
I
W
V
A
PK =+
=
37 5
9
0 524
1
0 380
2
947
.
.
Multiple Outputs
One advantage that the yback topology offers is that ad-
ditional output voltages can be obtained simply by adding
windings. Designing a transformer for such a situation is
beyond the scope of this document. For multiple windings,
realize that the yback winding signal is a combination of
activity on all the secondary windings. Thus load regulation
is affected by each windings load. Take care to minimize
cross regulation effects.
Setting Feedback Resistive Divider
Use the equation developed in the Operation section for
the feedback divider.
It is recommended that the Thevenin impedance of the
resistors on the FB Pin is roughly 3k for bias current
cancellation and other reasons.
For the example using primary winding sensing if
ESR = 0.002 and RDS(ON) = 0.004 then:
R
k
1
3
1 237
3 3 10
0 002 0 004
13
=
+
(
()
.
..
.
/
–
–.
.
0 7
22 75
=
k
So, choose 22.1k.
Current Sense Resistor Considerations
The external current sense resistor is used to control peak
primary switch current, which controls a number of key
converter characteristics including maximum power and
external component ratings. Use a noninductive current
sense resistor (no wire-wound resistors). Mounting the
resistor directly above an unbroken ground plane con-
nected with wide and short traces keeps stray resistance
and inductance low.
The dual sense pins allow for a fully Kelvined connection.
Make sure that SENSE+ and SENSE– are isolated and con-
nect close to the sense resistor to preserve this.
Peak current occurs at 98mV of sense voltage VSENSE. So
the nominal sense resistor is VSENSE/IPK. For example, a
peak switch current of 10A requires a nominal sense resistor
of 0.010
Ω. Note that the instantaneous peak power in the
sense resistor is 1W, and that it is rated accordingly. The
use of parallel resistors can help achieve low resistance,
low parasitic inductance and increased power capability.
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