參數(shù)資料
型號(hào)： LLT3837EFE
廠商： LINEAR TECHNOLOGY CORP
元件分類： 穩(wěn)壓器
英文描述： SWITCHING CONTROLLER, 110 kHz SWITCHING FREQ-MAX, PDSO16
封裝： 4.40 MM, PLASTIC, TSSOP-16
文件頁(yè)數(shù)： 13/28頁(yè)
文件大?。?/td> 255K
代理商： LLT3837EFE
LT3837
20
3837fa
If we wanted a VIN-referred trip point of 8.4V, with 0.3V
of hysteresis (on at 8.4V, off at 8.1V):
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Even with good board layout, board noise may cause
problems with UVLO. You can lter the divider but keep
large capacitance off the UVLO node because it will slow
the hysteresis produced from the change in bias current.
Figure 4c shows an alternate method of ltering by split-
ting the RA resistor with the capacitor. The split should
put more of the resistance on the UVLO side.
Control Loop Compensation
Loop frequency compensation is performed by connect-
ing a capacitor network from the output of the feedback
amplier (VC pin) to ground as shown in Figure 5. Be-
cause of the sampling behavior of the feedback amplier,
compensation is different from traditional current mode
switcher controllers. Normally only CVC is required. RVC
can be used to add a “zero” but the phase margin improve-
ment traditionally offered by this extra resistor is usually
already accomplished by the nonzero secondary circuit
impedance. CVC2 can be used to add an additional high
frequency pole and is usually sized at 0.1 times CVC.
APPLICATIONS INFORMATION
Figure 5. VC Compensation Network
9
RVC
VC
CVC
3825 F05
CVC2
In further contrast to traditional current mode switchers,
VC pin ripple is generally not an issue with the LT3837.
The dynamic nature of the clamped feedback amplier
forms an effective track/hold type response, whereby the
VC voltage changes during the yback pulse, but is then
“held” during the subsequent “switch on” portion of the
next cycle. This action naturally holds the VC voltage stable
during the current comparator sense action (current mode
switching).
AN19 provides a method for empirically tweaking frequency
compensation. Basically, it involves introducing a load
current step and monitoring the response.
Slope Compensation
This part incorporates current slope compensation. Slope
compensation is required to ensure current loop stability
when the DC is greater than 50%. In some switcher con-
trollers, slope compensation reduces the maximum peak
current at higher duty cycles. The LT3837 eliminates this
need by having circuitry that compensates for the slope
compensation so that maximum current sense voltage is
constant across all duty cycles.
Minimum Load Considerations
At light loads, the LT3837 derived regulator goes into
forced continuous conduction mode. The primary side
switch always turns on for a short time as set by the
tON(MIN) resistor. If this produces more power than the
load requires, power will ow back into the primary during
the “off” period when the synchronization switch is on.
This does not produce any inherently adverse problems,
though light load efciency is reduced.
Maximum Load Considerations
The current mode control uses the VC node voltage and
amplied sense resistor voltage as inputs to the current
comparator. When the amplied sense voltage exceeds the
VC node voltage, the primary side switch is turned off.
In normal use, the peak switch current increases while
FB is below the internal reference. This continues until
VC reaches its 2.56V clamp. At clamp, the primary side
MOSFET will turn off at the rated 98mV VSENSE level. This
repeats on the next cycle.
It is possible for the peak primary switch currents as
referred across RSENSE to exceed the max 98mV rating
because of the minimum switch on time blanking. If the
voltage on VSENSE reaches 206mV after the minimum
turn-on time, the SFST capacitor is discharged, which also
discharges the VC capacitor. This then reduces the peak
current on the next cycle and will reduce overall stress in
the primary switch.
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