參數(shù)資料
型號： LFXP2-17E-7F484C
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
中文描述： FPGA, 420 MHz, PBGA484
封裝： 23 X 23 MM, FPBGA-484
文件頁數(shù)： 91/92頁
文件大小： 1701K
代理商： LFXP2-17E-7F484C
August 2008
Data Sheet DS1009
2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
7-1
Revision History
Date
Version
Section
Change Summary
May 2007
01.1
—
Initial release.
September 2007
01.2
DC and Switching
Characteristics
Added JTAG Port Timing Waveforms diagram.
Updated sysCLOCK PLL Timing table.
Pinout Information
Added Thermal Management text section.
February 2008
01.3
Architecture
Added LVCMOS33D to Supported Output Standards table.
Clarified: “This Flash can be programmed through either the JTAG or
Slave SPI ports of the device. The SRAM configuration space can also
be infinitely reconfigured through the JTAG and Master SPI ports.”
Added External Slave SPI Port to Serial TAG Memory section. Updated
Serial TAG Memory diagram.
DC and Switching
Characteristics
Updated Flash Programming Specifications table.
Added “8W” specification to Hot Socketing Specifications table.
Updated Timing Tables
Clarifications for IIH in DC Electrical Characteristics table.
Added LVCMOS33D section
Updated DOA and DOA (Regs) to EBR Timing diagrams.
Removed Master Clock Frequency and Duty Cycle sections from the
LatticeXP2 sysCONFIG Port Timing Specifications table. These are
listed on the On-chip Oscillator and Configuration Master Clock Charac-
teristics table.
Changed CSSPIN to CSSPISN in description of tSCS, tSCSS, and tSCSH
parameters. Removed tSOE parameter.
Clarified On-chip Oscillator documentation
Added Switching Test Conditions
Pinout Information
Added “True LVDS Pairs Bonding Out per Bank,” “DDR Banks Bonding
Out per I/O Bank,” and “PCI capable I/Os Bonding Out per Bank” to Pin
Information Summary in place of previous blank table “PCI and DDR
Capabilities of the Device-Package Combinations”
Removed pinout listing. This information is available on the LatticeXP2
product web pages
Ordering Information
Added XP2-17 “8W” and all other family OPNs.
April 2008
01.4
DC and Switching
Characteristics
Updated Absolute Maximum Ratings footnotes.
Updated Recommended Operating Conditions Table footnotes.
Updated Supply Current (Standby) Table
Updated Initialization Supply Current Table
Updated Programming and Erase Flash Supply Current Table
Updated Register to Register Performance Table
Updated LatticeXP2 External Switching Characteristics Table
Updated LatticeXP2 Internal Switching Characteristics Table
Updated sysCLOCK PLL Timing Table
LatticeXP2 Family Data Sheet
Revision History
相關(guān)PDF資料
PDF描述
LFXP20E-3FN484C
LFXP20E-5FN484C
LFXP15C-4FN256C
LFZ3508VXX GENERAL PURPOSE INDUCTOR
LFZ2805HXX GENERAL PURPOSE INDUCTOR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LFXP2-17E-7F484C8W 功能描述:FPGA - 現(xiàn)場可編程門陣列 17KLUTs 358I/O Inst- on DSP 1.2V -7Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFXP2-17E-7FN484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 17KLUTs 358 I/O Inst -on DSP 1.2V -6 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFXP2-17E-7FN484C8W 功能描述:FPGA - 現(xiàn)場可編程門陣列 17KLUTs 358I/O Inst -on DSP 1.2V -7 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFXP2-17E-7FT256C 功能描述:FPGA - 現(xiàn)場可編程門陣列 17KLUTs 201 I/O Inst -on DSP 1.2V -7 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFXP2-17E-7FT256C8W 功能描述:FPGA - 現(xiàn)場可編程門陣列 17KLUTs 201 I/O Inst -on DSP 1.2V -7 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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