參數(shù)資料
型號: LFXP2-17E-7F484C
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: FPGA
中文描述: FPGA, 420 MHz, PBGA484
封裝: 23 X 23 MM, FPBGA-484
文件頁數(shù): 20/92頁
文件大小: 1701K
代理商: LFXP2-17E-7F484C
2-24
Architecture
Lattice Semiconductor
LatticeXP2 Family Data Sheet
register. Similarly, CE and RST are selected from their four respective sources (CE0, CE1, CE2, CE3 and RST0,
RST1, RST2, RST3) at each input register, pipeline register and output register.
Signed and Unsigned with Different Widths
The DSP block supports other widths, in addition to x9, x18 and x36 widths, of signed and unsigned multipliers. For
unsigned operands, unused upper data bits should be lled to create a valid x9, x18 or x36 operand. For signed
two’s complement operands, sign extension of the most signi cant bit should be performed until x9, x18 or x36
width is reached. Table 2-7 provides an example of this.
Table 2-7. Sign Extension Example
OVERFLOW Flag from MAC
The sysDSP block provides an overflow output to indicate that the accumulator has overflowed. “Roll-over” occurs
and an overflow signal is indicated when any of the following is true: two unsigned numbers are added and the
result is a smaller number than the accumulator, two positive numbers are added with a negative sum or two nega-
tive numbers are added with a positive sum. Note that when overflow occurs the overflow flag is present for only
one cycle. By counting these overflow pulses in FPGA logic, larger accumulators can be constructed. The condi-
tions for the overflow signal for signed and unsigned operands are listed in Figure 2-24.
Figure 2-24. Accumulator Over ow/Under ow
Number
Unsigned
9-bit
Unsigned
18-bit
Signed
Two’s Complement
Signed 9 Bits
Two’s Complement
Signed 18 Bits
+5
0101
000000101
000000000000000101
0101
000000101
000000000000000101
-6
N/A
1010
111111010
111111111111111010
000000000
000000001
000000010
000000011
111111101
111111110
111111111
Overflow signal is generated
for one cycle when this
boundary is crossed
0
+1
+2
+3
-3
-2
-1
Unsigned Operation
Signed Operation
255
254
253
252
-254
-255
-256
000000000
000000001
000000010
000000011
111111101
111111110
111111111
Carry signal is generated for
one cycle when this
boundary is crossed
0
1
2
3
509
510
511
255
254
253
252
258
257
256
011111100
011111101
011111110
011111111
100000000
100000001
100000010
011111100
011111101
011111110
011111111
100000000
100000001
100000010
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