參數(shù)資料
型號： LC89057W-VF4-E
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： 7 X 7 MM, SQFP-48
文件頁數(shù)： 8/61頁
文件大?。?/td> 355K
代理商： LC89057W-VF4-E
LC89057W-VF4-E
No. 7202-16/61
8.1.7 Output clocks (RMCK, RBCK, RLRCK, SBCK, SLRCK)
The LC89057W-VF4-E features two clock systems in order to supply the various needed clocks to the A/D
converter, DSP, and other peripheral devices.
The clock output settings for the R and S systems are done with PRSEL0,1, XRSEL0,1, XRBCK0,1, XRLRCK0,1,
PSBCK0,1, PSLRCK0,1, XSBCK0,1, and XSLRCK0,1.
(a) Setting range for clock output pins when using PLL source
(1) RMCK: Select from 1/1, 1/2, and 1/4 of 512fs or 256fs
(2) RBCK: 64fs output
(3) RLRCK: fs output
(4) SBCK: Select from 128fs, 64fs, and 32fs
(5) SLRCK: Select from 2fs, fs, and fs/2
(b) Setting range for clock output pins when using XIN source
(1) RMCK: Select from 1/1, 1/2, and 1/4 of 12.288MHz or 24.576MHz
(2) RBCK: Select from 12.288MHz, 6.144MHz, and 3.072MHz
(3) SBCK: Select from 12.288MHz, 6.144MHz, and 3.072MHz
(4) RLRCK: Select from 192kHz, 96kHz, and 48kHz
(5) SLRCK: Select from 192kHz, 96kHz, and 48kHz
The polarity of RBCK, RLRCK, SBCK, and SLRCK can be reversed with RBCKP, RLRCKP, SBCKP, and
SLRCKP.
Clock switching is processed from the rising edge of RLRCK output after the falling edge of microcontroller
interface CE.
Table 8.3. Output Clock Frequencies (Bold Items = Initial Settings)
PLL Source
TMCK Source
XIN Source
Output Pin Name
512fs
256fs
12.288MHz
24.576MHz
512fs
256fs
12.288MHz
24.576MHz
RMCK
256fs
128fs
6.144MHz
12.288MHz
128fs
64fs
3.072MHz
6.144MHz
12.288MHz
RBCK
64fs
6.144MHz
3.072MHz
192kHz
RLRCK
fs
96kHz
48kHz
128fs
12.288MHz
SBCK
64fs
6.144MHz
32fs
3.072MHz
2fs
192kHz
SLRCK
fs
96kHz
fs/2
48kHz
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