參數(shù)資料
型號： LC89057W-VF4-E
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： 7 X 7 MM, SQFP-48
文件頁數(shù)： 20/61頁
文件大?。?/td> 355K
代理商： LC89057W-VF4-E
LC89057W-VF4-E
No. 7202-27/61
8.4.6 Processing during error recovery
When preambles B, M, and W are detected, PLL becomes locked and data demodulation begins.
RDATA output data is output from the RLRCK edge after RERR goes "L".
RERR
RDATA
RLRCK
Data
45 ms to 300 ms
OK
Internal clock signal
Output start from RLRCK edge
immediately after RERR flag is lowered
Figure 8.12. Internal Lock Signal
8.5 Channel Status Output
8.5.1 Data category specification bit 1 output (AUDIO )
AUDIO outputs bit 1 of the channel status that indicates whether the input bi-phase data is PCM audio data. AUDIO
is immediately output upon detection of RERR even during "H" output.
ORed output with IEC61937 or the DTS-CD/LD detection flag is also possible with AOSEL.
Table 8.6. AUDIO Output
AUDIO
Output Conditions
0
PCM audio data (CS bit 1 = "L")
1
Non-audio data (CS bit 1 = "H"
8.5.2 Emphasis information output (EMPHA)
EMPHA outputs a signal that indicates the presence or absence of 50/15
s emphasis for consumer and broadcast
studio.
EMPHA is immediately output upon detection of RERR even during "H" output.
Table 8.7. EMPHA Output
EMPHA
Output Conditions
0
No pre-emphasis
1
50/15
s pre-emphasis
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