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參數(shù)資料
| 型號： | LC89057W-VF4-E |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 MM, SQFP-48 |
| 文件頁數(shù)： | 7/61頁 |
| 文件大?。?/td> | 355K |
| 代理商： | LC89057W-VF4-E |
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LC89057W-VF4-E
No. 7202-15/61
8.1.5 Cautions on switching clock source while PLL is locked
Clock continuity is maintained when switching the clock to the XIN source with SELMTD, OCKSEL, and
RCKSEL when the oscillation amplifier is stopped while the PLL is locked (initial setting), but RERR outputs an
error ("H") once. This is because, although the oscillation amplifier goes into the operating state at the same time
that the clock is switched to the XIN source, and calculation of the input fs (sampling frequency) resumes, the
previous fs calculation value is reset and processing is performed as if the fs value had changed compared to the
newly calculated fs value.
The following settings must be performed in order to switch the clock source with SELMTD, OCKSEL, and
RCKSEL while PLL is locked while maintaining the RERR status.
(1) Set the oscillation amplifier to the continuous operation mode with AMPOPR0,1.
(2) Set with FSERR the mode for not reflecting fs changes to the error flag.
By performing one of the above settings, it is possible to control the RERR change status when switching the clock
source with SELMTD, OCKSEL, and RCKSEL.
When switching the clock source to XIN from the status where the oscillation amplifier is stopped while the PLL is
locked, the output clock using XIN as the source is output after the oscillation amplifier starts operating. Switching
of the clock source from XIN to PLL when the PLL is locked is performed instantaneously, and clock continuity is
maintained in either case.
8.1.6 Master clock block diagram (TMCK, XIN, XOUT, RMCK, XMCK)
The relationships between the three master clocks, switching, and the frequency division function, are shown.
The contents in the square brackets [
] by the switch function blocks correspond to the write command names.
Lock/Unlock switching is automatically performed through PLL locking/unlocking.
PLL
1/N
(256fs or 512fs)
Selected Biphase
TMCK (I) 256fs only
XIN (I)
XOUT (O)
RMCK (O)
XMCK (O)
[EXSYNC]
[RCKSEL]
[PLLOPR]
[PLLSEL]
[PRSEL1]
[XRSEL1]
[XINSEL]
[XMSEL1]
[AMPOPR1]
(N=1, 2)
Lock /Unlock
1/N
(N=1, 2)
1/N
(N=1, 2, 4)
1/N
(N=1, 2, 4)
[OCKSEL]
[XMSEL0]
[XRSEL0]
[PRSEL0]
[SELMTD]
[AMPOPR0]
Figure 8.2. Master Clock Block Diagram
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LC89058W | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:CMOS IC Digital Audio Interface Receiver |
| LC89058WA-E | 功能描述:音頻發(fā)送器、接收器、收發(fā)器 RoHS:否 制造商:Cirrus Logic 工作電源電壓:3.3 V, 5 V 電源電流:11.8 mA 通道數(shù)量:1 最大工作溫度:+ 70 C 接口類型:I2C, SPI 安裝風格:SMD/SMT 封裝 / 箱體:TSSOP-28 封裝: |
| LC89058W-E | 功能描述:音頻 DSP AUDIO INTERFACE RECEIVER RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| LC8905V | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Digital Audio Interface Receiver |
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