參數(shù)資料
型號: LC890561W
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝: 7 X 7 MM, SQFP-48
文件頁數(shù): 7/47頁
文件大?。?/td> 357K
代理商: LC890561W
LC890561W
No8226-15/47
12.4 Output Clock (CKOUT, BCK, LRCK)
The CKOUT output clock is selected by setting CKSEL0 and CKSEL1 terminals.
Table 12.4 CKOUT Output Clock Selection
CKSEL1 pin
CKSEL0 pin
CKOUT pin
0
256fs output
0
1
384fs output
1
0
512fs output
1
512fs/2 output
256fs must be chosen when receiving data over 96kHz as above table. There is no restriction of selection for data
reception under 96kHz.
512fs/2 set PLL band as 512fs, and CKOUT clock outputs one half (256fs output).
64fs clock (64fs only) is outputted from BCK, and the fs clock is outputted from LRCK.
When PLL is unlocked, the XIN and XOUT oscillation amplifier clock or the external input clock is output from
CKOUT, and the divided clock of this clock is outputted from BCK and LRCK.
Output of 1/2 CKOUT clock by CKDV command is possible.
Reverse of the polarity of CKOUT clock by CKPO command is also possible.
In the PLL lock and unlock phases, the CKOUT (BCK and LRCK likewise) clock switch timing is as follows.
Figure 12.1 Output Clock Switch Timing
DIN0 to DIN2
PLL lock state
XIN clock
VCO clock
XSTATE
ERROR
CKOUT
(a): During lock-in phase
Digital data
UNLOCK
LOCK
1ms to 276ms
Digital data
LOCK
UNLOCK
5ms to 12ms
DIN0 to DIN2
PLL lock state
XIN clock
VCO clock
XSTATE
ERROR
CKOUT
(b): During unlock phase
Same
(XSTP = 0)
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