參數(shù)資料
型號(hào): LC890561W
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝: 7 X 7 MM, SQFP-48
文件頁(yè)數(shù): 10/47頁(yè)
文件大?。?/td> 357K
代理商: LC890561W
LC890561W
No8226-18/47
12.5.3 Output Data Changing (DATAO, DATAO2, SDIN)
DATAO and DATAO2 output demodulation data when PLL is locked, and output SDIN input data when PLL is
unlocked. This switching is automatically performed according to the state of PLL lock or unlock.
During the selection of SDIN input data, it must be switched to the clock source that is in synchronized with SDIN data.
SDIIN input data is output to DATAO and DATAO2 with the SMOD command setting regardless of the lock /
unlock state of PLL. In the case of switching PLL in the lock state, clock source is also switched to XIN. Furthermore,
an ERROR flag also outputs high and a XSTATE signal also changes.
DATAO and DATAO2 output can be muted forcibly with setting of the DOM[1:0] commands.
Figure 12.4 DATAO and DATAO2 Outputs Data Chang Timing Charts
12.5.4 Data System Diagram (DIN0, DIN1, DIN2, SDIN, DOUT, DATAO, DATAO2)
Data system diagram is shown below.
The delay setup for DATAO is possible. However, the delay setup for DATAO2 is impossible because DATAO2
does not go through a memory.
DIN0 to DIN2 and SDIN input data are output to DATAO and DATAO2 behind two frames. Delay setup of output
data is processed with the DATAO output with 2-frame delay against the input data as delay for 0ms.
Since DATAO2 shares the pin with the validity flag output, it should be changed by the VSEL command. The initial
value of VSEL is the validity flag output.
Figure 12.5 Data System Diagram
DIN0
MUX
(3in/1out)
DIR
DIN1
DIN2
SDIN
DATAO
DOUT
[SMOD]
Buffer
RAM
VF/DATAO2
Data register
[VSEL]
VF
PLL state
XSTATE
ERROR
(a): Lock-in stage
UNLOCK
LOCK
(b): Unlock stage
SDIN data
Muted
Demodulation data
PLL state
DATAO
XSTATE
ERROR
LOCK
UNLOCK
SDIN data
Muted
Demodulation data
DATAO
DATAO2
(XSTP = 0)
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