參數(shù)資料
型號(hào): LC890561W
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝: 7 X 7 MM, SQFP-48
文件頁數(shù): 15/47頁
文件大?。?/td> 357K
代理商: LC890561W
LC890561W
No8226-22/47
12.10 First 48 Channel Status Bits Update Flag Output (CSFLAG)
CSFLAG compares the first 48 bits of channel status data of the previous block with those of the current block and
outputs low in case they are the same, and high in case they are different, for 1 block of 192 frames. Therefore the
channel status data output after the falling edge of the CSFLAG is the latest data.
CSFLAG outputs high regardless of the comparison result until ERROR outputs low. After ERROR output becomes
low, CSFLAG outputs low after the first 48bit data of the previous data and the current data have been confirmed to
be identical.
Table 12.9 CSFLAG Output
CSFLAG pin
Output condition
L
Previous data current data are identical
H
Previous data differs from current data
Figure 12.9 Timing Chart for Channel Status Update Flag Output
12.11 Non-PCM Burst Preamble Detection Signal Output (BPSYNC)
BPSYNC outputs low while Non-PCM burst preamble Pa, Pb, Pc and Pd output, when Pa and Pb are detected
following continuous all zero data of two frame. However, when output data delay is set up, low period of a BPSYNC
signal and the output period of the Non-PCM burst preamble Pa, Pb, Pc, and Pd do not match. In this case, BPSYNC
is output ahead of Pa, Pb, Pc, and Pd data.
Pa, Pb, Pc and Pd are detected from the receive data even when an input parity error occurs.
Figure 12.10 Timing Chart for Pa, Pb, Pc and Pd Detection Signal Output
M191
Input data
LRCK
CSFLAG
Become “H” when not identical to previous block
W191
B
W
W46
W47
W48
M47
M49
M48
M50
W49
bit 191
bit 0
bit 46
bit 47
bit 48
bit 49
bit 50
000h
Input data
Preamble
DATAO
LRCK
BPSYNC
000h
000h 000h
Pa
Pb
Pc
Pd
2
3
4
Pa
Pb
Pc
Pd
2
Burst payload
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LC89057W-VF4AD-E 制造商:ON Semiconductor 功能描述:
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