參數(shù)資料
型號: LC890561W
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝: 7 X 7 MM, SQFP-48
文件頁數(shù): 25/47頁
文件大小: 357K
代理商: LC890561W
LC890561W
No8226-31/47
13.4 Monitor Setup for Output Data Delay Setting (FSEL)
Information available for delay setting of output data can be monitored by FSB0, FSB1 and DLMP pins by switching
the FSEL command. This setup is switched by FSEL command.
FSB0 and FSB1 terminal classifies the calculation result of the sampling frequency of input data into standard
frequency, standard
×2, and standard ×4 and outputs.
However, when S/PDIF data is not received, PLL is not locked, or when the mode 4 is set up with MODE0 and
MODE1 terminal, FSB0 and FSB1 terminals output low.
DLMP terminal outputs a pulse signal during the waiting time period at the time of ERROR flag switching, or during
the mute period at the time of a delay setup. This pulse can change polarity by DLPO command.
Table 13.3. FSB0 and FSB1 output state (FSEL = 1)
FSB1 pin
FSB0 pin
Output state
L
S/PDIF data is not received, or PLL is unlocked, when the mode 4 is set up with
MODE0 and MODE1 terminal.
L
H
S/PDIF data is either of the 32kHz or 44.1kHz or 48kHz.
(Standard frequency)
H
L
S/PDIF data is either of the 88.2kHz or 96kHz.
(Standard
×2 frequency)
H
S/PDIF data is either of the 176.4kHz or 192kHz.
(Standard
×4 frequency)
Figure 13.10 Timing Chart for DLMP Output Mute Period (command cancel is not included)
XSTATE
DATAO
Recovery
ERROR
Recovery
DLMP
Mute
(XSTP = 0)
DLMA to B
State
DLMX, Y
State
SDIN
Recovery
Mute = Delay time
Mute
Mute = Delay time
Delay time
DATAO2
Recovery
SDIN
Recovery
(DLPO = 0)
Delay setting of SDIN
Delay setting of recovery data
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