參數(shù)資料
型號: LC890561W
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝: 7 X 7 MM, SQFP-48
文件頁數(shù): 21/47頁
文件大小: 357K
代理商: LC890561W
LC890561W
No8226-28/47
13.2.3 Output Data Delay Setup of SDIN Input Data (Setting at the state of ERROR = L)
When the DTMX[4:0] or DTMY[3:0] commands are set up during low output of ERROR flag, data is written to a
memory in synchronization with the rising edge of XSTATE after PLL unlock.
Readout of the data written in the memory is started after the set delay time (frame).
The data read out is constantly output form DATAO with the delay of the setup time.
DATAO will be muted until the set delay time is over, because sufficient data is not written into memory immediately
after the low output of ERROR flag.
Figure 13.5 Timing Chart for Output Data after Setup or Change of the Delay Time During PLL Unlock
When the DTMX[4:0] or DTMY[3:0] commands are canceled during low output of ERROR flag, data is output from
DATAO synchronizing with the rising edge of XSTATE after PLL unlock. This is normal operation which does not
perform a delay processing setup.
Figure 13.6 Timing Chart for Output Data after Cancel of the Delay Time Setting During PLL Unlock
DIN*
Lock state
ERROR
Mm-1
DATAO
Wm-1
Wm
Lock
Unlock
0 data (mute)
DATAO2
Recovery data
0 data (mute)
Recovery data
Mm
XSTATE
SDIN
Ln-2 Rn-1
Rn
Ln-1
Ln
R1
L1
R2
L2
L3
Ro
Lo
Ro+1
Lo+1
R0
L0
Lo-1
Ro-2
Lo
Ro-1
R0
L0
L1
Wait period:
5ms to 12ms
Delay time
(XSTP = 0)
DIN*
Lock state
ERROR
Mm-1
DATAO
Wm-1
Wm
Lock
Unlock
0 data (mute)
DATAO2
Recovery data
0 data (mute)
Recovery data
Mm
XSTATE
SDIN
Ln-2 Rn-1
Rn
Ln-1
Ln
R1
L1
R2
L2
L3
Ro
Lo
Ro+1
Lo+1
R0
L0
Lo-1
Ro-2
Lo
Ro-1
Wait period:
5ms to 12ms
(XSTP = 0)
R0
L0
Lo-1
Ro-2
Lo
Ro-1
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