參數(shù)資料
型號(hào): LC78628E
廠商: Sanyo Electric Co.,Ltd.
元件分類: 數(shù)字信號(hào)處理
英文描述: 16-bit fixed point DSP with Flash
中文描述: 具有閃存的 16 位定點(diǎn) DSP
文件頁數(shù): 29/40頁
文件大?。?/td> 241K
代理商: LC78628E
No. 6329-29/40
LC78628E
Normal speed: 1/44.1 kHz, 2
×
speed: 1/88.2 kHz
Rch
18
LSB
MSB
1716151413121110 9 8 7 6 5 4 3 2 1
LSB
MSB
18171615
13
14
121110 9 8 7 6 5 4 3 2 1
LSB
Lch
DATAI
LRCKI
BCKI
A12829
Normal speed: 1/44.1 kHz, 2
×
speed: 1/88.2 kHz
Rch
LSB
151413121110 9 8 7 6 5 4 3 2 1
LSB
MSB
13
14
121110 9 8 7 6 5 4 3 2 1
LSB
Lch
DATAI
LRCKI
BCKI
A12830
0
1
2
3
4
5
6
7
COIN
CQCK
RWC
A12831
Timing when 20-bit data is input to IC pins
Timing when 16-bit data is input to IC pins
Use 20-bit input mode when inputting, to the LRCKI, BCKI, and DATAI pins, post-HDCD decoding 20-bit data that
was recorded on MD and using this IC’s internal D/A converter for playback.
When the HDCD filter block input source is set to pin input by setting XDSEL flag to 1, do not set the IC to CD
playback state. In this case, if gain scaling is set to analog gain scaling mode, the GAIN pin will output a low level,
and if set to digital gain scaling mode, it will output a high level.
Clocks applied to the LRCKI and BCKI pins must be synchronized with the LC78628E’s system clock.
HDCD Control Register (CRHDCD)
The HDCD control register consists of 6 flags used for setting the modes associated with HDCD operations. This section
presents the method for setting this register and the meanings of the flags.
Setting procedure
The HDCD control register is set using the following 2-byte command.
Instruction code: $D8xx (2-byte command)
Here, xx corresponds to the flags in CRHDCD, and bits transferred as a high level are set to 1.
相關(guān)PDF資料
PDF描述
LC78630 16-bit fixed point DSP with Flash
LC78630E 16-bit fixed point DSP with Flash
LC78631 16-bit fixed point DSP with Flash
LC78631E 16-bit fixed point DSP with Flash
LC78632 16-bit fixed point DSP with Flash
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