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參數(shù)資料
| 型號： | LC78628E |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-bit fixed point DSP with Flash |
| 中文描述： | 具有閃存的 16 位定點(diǎn) DSP |
| 文件頁數(shù)： | 11/40頁 |
| 文件大?。?/td> | 241K |
| 代理商： | LC78628E |
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No. 6329-11/40
LC78628E
Internal Functions
1. HF signal input circuit — Pin 11: EFMIN, pin 10: EFMO, pin 1: DEFI, pin 13: CLV
+
When an HF signal is input to the EFMIN pin, an
EFM signal (NRZ) sliced at the optimal level is
acquired. As a measure to handle defects, when the
DEFI pin (pin 1) goes high, the slice level
controller output from the EFMO pin (pin 10) goes
to the high-impedance state, and the slice level is
held. However, this is only valid when the CLV
circuit is in phase control mode, that is, when the
V/P pin (pin 15) is outputting a low level.
This function can be implemented in combination
with the DEF pin from an LA9230/9240 series
product.
*: If the EFMIN and CLV
+
lines are run close
together, the error rate may increase due to
spurious radiation. We recommend inserting
either a ground or V
DD
shield line between these
lines.
2. PLL clock regeneration circuit — Pin 3: PDO, pin 5: ISET, pin 7: FR, pin 21: PCK
The LC78628E includes a built-in VCO circuit,
and a PLL circuit is formed by adding external
resistors and capacitors. The ISET pin sets the
charge pump reference current, PDO sets the VCO
circuit loop filter, and FR sets the VCO frequency
range.
Sample values for reference purposes:
R1 = 68 k
, C1 = 0.1 μF
R2 = 680
, C2 = 0.1 μF
R3 = 1.2 k
+
–
SLC
SLI
VREF
11
10
EFMIN
EFMO
HF signal
A12803
VDD
R1
C2
R2
R3
C1
5 ISET
EFM(NRZ)
PDO
FR
PCK
VCO
1/N
Charge pump
Frequency
and phase
comparator
3
21
7
A12804
Code
Command
VCO
×
2 SET
VCO
×
1 SET
VCO
×
0.5 SET
Frequency divisor
RES = low
$AC
1
$AD
2
$AE
0.5
G
G
The divisor used by the divider to create PCK from the VCO can be set using the VCO
×
2, VCO
×
1, and VCO
×
0.5 SET instructions. Normally, the circuit
operates in the VCO
×
0.5 SET state after a reset.
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