參數(shù)資料
型號： LC78626E
廠商： Sanyo Electric Co.,Ltd.
元件分類： 數(shù)字信號處理
英文描述： 16-bit fixed point DSP with Flash
中文描述： 具有閃存的 16 位定點 DSP
文件頁數(shù)： 9/32頁
文件大?。?/td> 475K
代理商： LC78626E
No. 5692-9/32
LC78626E
Description of Pins
Pin
No.
Pin
Name
I/O
Function
1
DEFI
I
Defect detection signal (DEF) input. When not used, must be connected to 0 V.
2
TAI
I
Test input. Equipped with internal pull-down resistor. Must be connected to 0V.
3
PDO
O
External VCO control phase comparator output.
4
VV
SS
ISET
P
For the PLL
Internal VCO ground. Must be connected to 0 V.
5
AI
PDO output current adjustment resistor connection.
6
VV
DD
FR
P
Internal VCO power supply.
7
AI
VCO frequency range adjustment
8
V
SS
TESCLK
P
Digital system ground. Must be connected to 0 V.
9
I
Test clock input. Must be connected to VDD.
10
TESA
I
Test operation mode control input. Must be connected to VDD.
11
TESB
I
Test operation mode control input. Must be connected to VDD.
12
TESC
I
Test operation mode control input. Must be connected to VDD.
13
TESGB
I
Test operation mode control input. Must be connected to VDD.
14
TEST5
I
Test input. Equipped with internal pull-down resistor. Must be connected to 0 V.
15
CS
I
Chip select input. Equipped with internal pull-down resistor. When not controlled, must be connected to 0 V.
16
TEST1
I
Test input. Must be connected to 0 V.
17
EFMO
O
For slice
EFM signal output.
18
EFMI
I
level control.
EFM signal input.
19
TEST2
CLV
+
CLV
–
I
Test input. Equipped with internal pull-down resistor. Must be connected to 0 V.
20
O
Disk motor control output. Can have a 3-state output depending on the command.
21
O
22
V/P
O
Rough servo/phase control automatic switching monitor output. If a high level then rough servo mode. If a low level then
phase control mode.
23
HFL
I
Track detect signal input. Schmidt input.
24
TES
I
Tracking error signal input. Schmidt input.
25
TOFF
O
Tracking off output.
26
TGL
JP
+
JP
–
O
Tracking gain switch output. Gain is increased with low level.
27
O
Track jump control output. Can be 3-state output depending on the command.
28
O
29
PCK
O
EFM data playback clock monitor. 4.3218 MHz during phase lock.
30
FSEQ
O
Sync signal detect output. A high level when the sync signal detected from the EFM signal matches the internally
generated sync signal.
31
V
DD
P
Digital system power supply.
Reset signal input for initializing only the anti-shock control part (i.e. excluding the DSP part). Resets when this
pin is low level, and release the reset when this pin is high level. Tie this pin to the low level (i.e., connected to 0 V) if
when using software control on the anti-shock part alone through the anti-shock part only reset disable/release
I(I/O) command ($F4) or the anti-shock only reset enable/inrush command ($F5).
Note: This pin is assigned as the least significant bit of the general I/O port however, use as a general I/O
pin is disabled. When the port I/O set command ($DB) is executed, the least significant bit is always “0,” and the
output driver is not turned ON.
32
ASRES
33
CONT2
I/O
General I/O pin 2. This controls the commands from the microcontroller. When not used, either set this as an input
port and connect to 0 V, or set this as an output port and leave it open.
Continued on next page.
相關PDF資料
PDF描述
LC78628 16-bit fixed point DSP with Flash
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相關代理商/技術參數(shù)
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