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參數(shù)資料
| 型號： | LC78626E |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-bit fixed point DSP with Flash |
| 中文描述： | 具有閃存的 16 位定點 DSP |
| 文件頁數(shù)： | 11/32頁 |
| 文件大?。?/td> | 475K |
| 代理商： | LC78626E |
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No. 5692-11/32
LC78626E
Continued from preceding page.
PIn
No.
Pin
Name
I/O
Description
70
MMC0
O
Remaining DRAM output.
71
MMC1
O
Remaining DRAM output.
72
MMC2
O
Remaining DRAM output.
73
MMC3
O
Remaining DRAM output.
74
OVF
O
DRAM write terminated. (An RZP pulse is output when there is an overflow or a shock.)
75
CNTOK
O
Data contact point detection complete signal: low
→
high: detection complete. (DRAM write start).
DRAM write enable signal input: high: write enable.
76
WOK
I
77
PAUSE IN
I
Pause signal input: high: pause.
C2F data contact point detection start signal: low
→
high: detection start.
Remaining DRAM alarm output: low: memory low.
78
NGJ
O
79
EMPN
O
80
SHOCK
I
C2F shock detect pause signal input: low: pause shock detection.
81
DRAM3
I/O
DRAM data bus
82
DRAM2
I/O
DRAM data bus
83
DRAM1
I/O
DRAM data bus
84
DRAM0
I/O
DRAM data bus
85
OE
O
DRAM control signal.
86
WE
O
DRAM control signal.
87
CAS
O
DRAM control signal.
88
RAS
O
DRAM control signal.
89
AD9
O
DRAM address bus
90
AD8
O
DRAM address bus
91
AD7
O
DRAM address bus
92
AD6
O
DRAM address bus
93
AD5
O
DRAM address bus
94
V
SS
AD4
P
Digital system ground. Must be connected to 0 V.
95
O
DRAM address bus
96
AD3
O
DRAM address bus
97
AD2
O
DRAM address bus
98
AD1
O
DRAM address bus
99
AD0
O
DRAM address bus
100
V
DD
P
Digital system power supply.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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| LC78628E | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Compact Disc Player DSP with Built-in HDCD Decoder |
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