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參數(shù)資料
| 型號： | L9942XPTR |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 運(yùn)動控制電子 |
| 英文描述： | STEPPER MOTOR CONTROLLER, 2.5 A, PDSO24 |
| 封裝： | LEAD FREE, POWER, SSO-24 |
| 文件頁數(shù)： | 21/40頁 |
| 文件大?。?/td> | 664K |
| 代理商： | L9942XPTR |
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Logic with SPI - Electrical Characteristics
L9942
6
Logic with SPI - Electrical Characteristics
VS = 7 to 20 V, VCC = 3.0 to 5.3 V, EN=VCC, Tj = -40 to 150 °C, IREF = -200 μA, unless
otherwise specified. The voltages are referred to GND and currents are assumed positive,
when the current flows into the pin.
6.1
Inputs: CSN, CLK, STEP, EN and DI
6.2
DI timing
Table 20.
Inputs: CSN, CLK, STEP, EN and DI
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Vin L
input low level
0.3*VCC
0.4*VCC
V
Vin H
input high level
0.6*VCC
0.7*VCC
V
Vin Hyst
input hysteresis
0.1*VCC
V
ICSN in
pull up current at input CSN
VCSN = VCC-1.5 V,
-50
-25
-10
A
ICLK in
pull down current at input CLK
VCLK = 1.5 V
10
25
50
A
IDI in
pull down current at input DI
VDI = 1.5 V
10
25
50
A
ISTEP in
pull down current at input STEP
VSTEP = 1.5 V
10
25
50
A
REN in
resistance at input EN to GND
VEN in = VCC
110
510
k
Ω
Cin
(1)
input capacitance at input CSN,
CLK, DI and PWM
0 V < VCC < 5.3 V
10
15
pF
1.
Parameter guaranteed by design.
Table 21.
DI timing (see Figure 11 and Figure 13) (1)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
tCLK
clock period
VCC = 5 V
250
ns
tCLKH
clock high time
VCC = 5 V
100
ns
tCLKL
clock low time
VCC = 5 V
100
ns
tset CSN
CSN set up time, CSN low before
rising edge of CLK
VCC = 5 V
100
ns
tset CLK
CLK set up time, CLK high before
rising edge of CSN
VCC = 5 V
100
ns
tset DI
DI set up time
VCC = 5 V
50
ns
thold DI
DI hold time
VCC = 5 V
50
ns
tr in
rise time of input signal DI, CLK,
CSN
VCC = 5 V
25
ns
tf in
fall time of input signal DI, CLK, CSN VCC = 5 V
25
ns
1.
DI timing parameters tested in production by a passed/failed test:
Tj=-40°C/+25°C: SPI communication @5MHz; Tj=+125°C: SPI communication @4.25MHz
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