參數(shù)資料
型號： L9942XPTR
廠商： STMICROELECTRONICS
元件分類： 運(yùn)動控制電子
英文描述： STEPPER MOTOR CONTROLLER, 2.5 A, PDSO24
封裝： LEAD FREE, POWER, SSO-24
文件頁數(shù)： 15/40頁
文件大小： 664K
代理商： L9942XPTR
Functional Description of the Logic with SPI
L9942
Note:
Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel
operation of the SPI bus by controlling the CSN signal of the connected ICs is
recommended.
4.6
Serial Data Out (DO)
The data output driver is activated by a logical low level at the CSN input and will go from
high impedance to a low or high level depending on the status bit 0 (fault condition). The first
rising edge of the CLK input after a high to low transition of the CSN pin will transfer the
content of the selected status register into the data out shift register. Each subsequent
falling edge of the CLK will shift the next bit out.
4.7
Serial Clock (CLK)
The CLK input is used to synchronize the input and output serial bit streams. The data input
(DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the
falling edge of the CLK signal.
4.8
Data Register
The device has eight data registers. The first three bits (bit0 ... bit2) at the DI-input are used
to select one of the input registers. All bits are first shifted into an input shift register. After
the rising edge of CSN the contents of the input shift register will be written to the selected
Input Data Register only if a frame of exact 16 data bits are detected. The selected register
will be transferred to DO during the current communication frame.
Figure 9.
SPI and Registers
D
DI
CLK_ADR
D1
A1
D0
A2
D3
D4
D5
D6
D7
D8
D9
D10
D11
DO
DIR
Control Register 0
AI0
AI1
AI2
AI3
AI4
BI0
BI1
BI2
BI3
BI4
DAC Phase B
DAC Phase A
Counter and Profiles Register 2
P0
P1
P2
P3
P4
Phase
A
Phase
B
Status Register 7
D2
D12
Phase Counter
Control Register 1
I0
I1
I2
I3
I4
I0
I1
I2
I3
I4
Current Profile 0
Current Profile 1
T2
Test
Openload
LSA1
HSA1
LSA2
HSA2
LSB1
LSB2
HSB1
HSB2
Overcurrent
UV
OV
CSN
CLK
INT_2MHz
SPI-
Controll
POR
Slew Rate
Step Mode
SR0
SR1
ST1
ST0
DAC_Scale
DC1
DC2
Temperature
VS Monitor
SEL_ERROR
SPI2REG
D
A1
A0
A2
TSD
TW
RREF
Error
CLR
Status
CLR
Status
Read-Only
DC0
Read Only
PWM
Freq
Filter
I0
I1
I2
I3
I4
Current Profile 8
Read-Only
ST
I0
I1
I2
I3
I4
I0
I1
I2
I3
I4
Current Profile 2
Current Profile 3
NPWM
T3
T4
T5
Test
I0
I1
I2
I3
I4
I0
I1
I2
I3
I4
Current Profile 4
Current Profile 5
I0
I1
I2
I3
I4
I0
I1
I2
I3
I4
Current Profile 6
Current Profile 7
Decay Mode
DM0
DM1
DM2
SST
A0
PWM Counter
PWM
Test
PWM Counter
DT5
DT6
DT7
DT2
DT3
DT4
DT0
DT1
Singnal and Profiles Register 3
Counter and Profiles Register 4
Counter and Profiles Register 5
Control, Status and Profile
Register 6
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