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參數(shù)資料
| 型號(hào)： | L9352-DIE1 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | INTELLIGENT QUAD 2X5A/2X2.5A LOW-SIDE SWITCH |
| 中文描述： | 智能四2X5A/2X2.5A低邊開關(guān) |
| 文件頁數(shù)： | 9/21頁 |
| 文件大?。?/td> | 328K |
| 代理商： | L9352-DIE1 |
9/21
L9352
The ON period of the input signal is measured with a 1MHz clock, synchronized with the external 250kHz clock.
For requested precision of the output current the ratio between the frequencies of the input signal and the ex-
ternal 250kHz clock has to be fixed according to the graph shown in Fig.
Figure 4. Current accuracy according to the input and clock frequency ratio
The theoretical error is zero for f
CLK
/ f
IN
= 125.
If the period of the input signal is longer than 132 times the period of the clock the regulator is switched off. For
a clock frequency lower than 100kHz the clock control will also disable the regulator. For high precision appli-
cations the clock frequency and the input frequency have to be correlated.
The output current is measured during the recirculation of the load. The current sense resistor is in series to the
free wheeling diode. If this recirculation path is interrupted the regulator stops immediately and the status output
remains low for the rest of the input cycle.
The output period is 64 times the clock period. With a clock frequency of 250kHz the output PWM frequency is
3.9kHz. The output PWM is synchronized with the first negative edge of the input signal. After that the output
and the input are asynchronous. The first period is used to measure the current. This means the first turn-on of
the power is 256
μ
s after the first negative edge of the input signal.
As regulator a digital PI-regulator with the Transfer function for:
KI:
and KP: 0.96
for a sampling time of 256us is realised.
To speed up the current settling time the regulator output is locked to 90% output PWM untill the target current
value is reached. This happens alsowhen the target current value changes and the output PWM reaches 90%
during the regulation. The status output gets low if the target current value is not reached within the regulation
error delay time of
t
RE
=10ms. The output PWM is than out of the regulation range from 10% to 90%.
1.5
The outputs are protected against current overload, overtemperature, and power-GND-loss. The external clock
is monitored by a clock watchdog. This clock watchdog detects a minimal frequency
f
CLK,min
and wrong clock
duty cycles. The allowed clock duty cycle range is 45% to 55%. The current-regulator stages are protected
Protective Circuits
-10%
5.6%
112.5
132
125
f
CLK
/ f
IN
0%
c
Regulator
switched off
–
1
--------------
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|---|---|
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| L9380 | Triple High-Side MOSFET Driver(三高邊MOSFET驅(qū)動(dòng)器) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| L9353M | 制造商:EPCOS 制造商全稱:EPCOS 功能描述:IF Filter for Audio Applications |
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| L9360 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Injector Driver |
| L9360D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Injector Driver |
| L9360M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Injector Driver |
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