
L9352
6/21
Additional Diagnostic Functions channel 3 and channel 4 (regulated channels)
DC
OUT
Output duty cycle range
filtered with 10ms
10
90
%
I
QO3,4
Overload current 
channel 3,4 
V
S
≥
 6.5V
2.5
5
8
A
V
rerr
Recirculation error shutdown
threshold (open D3/D4)
Iout > 50mA
45
50
60
V
PWM
dOU
T
Output PWM ratio during drift 
comparison
V
IN3
 = V
IN4
 = PWM
IN
V
TEST
 = H 
-14.3
+14.3
%
Digital Inputs (IN1 to IN4, ENA, CLK, TEST). The valid PWM-Ratio for IN3/IN4 is 10% to 90%
V
IL
Input low voltage
-0.3
1
V
V
IH
Input high voltage
2
6
V
V
IHy
Input voltage hysteresis
(1)
20
500
mV
I
I
Input pull down current
V
IN
 = 5V, V
S
≥
 6.5V
8
20
40
μ
A
Digital Outputs (ST1 to ST4)
V
STL
Status output voltage in low state 
(2))
I
ST
≤
 40
μ
A
0
0.4
V
V
STH
Status output voltage in high state
 (2)
I
ST
≥
 -40
μ
A
2.5
3.45
V
I
ST
≥
 -120
μ
A
2
3.45
V
R
DIAGL
R
OUT
 + R
DSON
 in low state
0.3
0.64
1.5
k
R
DIAGH
R
OUT
 + R
DSON
 in high state
1.5
3.2
7.0
k
Power Outputs (Q1 to Q4)
R
DSON
Static drain-source ON-resistance
I
Q
 = 1A; V
S
≥
 9.5V
0.2
0.4
V
F_250mA
 Forward voltage of free wheeling path 
D3, D4 @250mA
I
D3/4
 = -250mA
0.5
1.5
V
V
F_2.25A
 Forward voltage of free wheeling path 
D3, D4 @2.25A
I
D3/4
 = -2.25A
2.0
4.5
V
R
sens
Sense resistor = (V
F_2.25A-
V
F_250mA
)/
2A
1
V
Z
Z-diode clamping voltage
I
Q
≥
 100mA
45
60
V
I
PD
Output pull down current
V
EN
 = H, V
IN
 = L
10
150
μ
A
I
Qlk
Output leakage current
V
EN
 = L; V
Q
 = 20V
5
μ
A
Timing
t
ON
Output ON delay time
I
Q
 = 1A
0
5
20
μ
s
t
OFF
Output OFF delay time channel
I
Q
 = 1A
0
10
30
μ
s
t
OFFREG
Output OFF delay time regulator
(3)
528
μ
s
t
r
Output rise time
I
Q
 = 1A
0.5
1.5
8
μ
s
ELECTRICAL CHARACTERISTCS
: 
 (continued)
(Vs = 4.8 to 18V; T
j
 = -40 to 150°C unless otherwise specified)
Symbol
Parameter
Test Condition
Min. 
Typ.
Max.
Unit