參數(shù)資料
型號(hào)： L9352-DIE1
廠商： 意法半導(dǎo)體
英文描述： INTELLIGENT QUAD 2X5A/2X2.5A LOW-SIDE SWITCH
中文描述： 智能四2X5A/2X2.5A低邊開關(guān)
文件頁(yè)數(shù)： 10/21頁(yè)
文件大?。?/td> 328K
代理商： L9352-DIE1
L9352
10/21
against recirculation errors, when D3 or D4 is not connected. All these error conditions shut off the power stage
and invert the status output information.
1.6
The status outputs indicate the switching state under normal conditions (status LOW = OFF; status HIGH = ON).
If an error occurs, the logic level of the status output is inverted, as listed in the diagnostic table below. All ex-
ternal errors, for example open load, are filtered internally. The following table shows the detected errors, the
filter times and the detection mode (on/off).
ON State
EN &IN = HIGH
EN &IN = LOW
Short circuit of the load
X
Error Detection
EN&IN=low means that at least one between enable and input is low. For the inputs IN=low means also no input
PWM. For the regulator input period longer than T
Dreg
and for the standard channel input period longer thanT
D
.
A detected error is stored in an error register. The reset of this register is made with a timer T
D
. With this ap-
proach all errors are present at the status output at least for the time T
D
.
All protection functions like short circuit of the output, overtemperature, clock failure or power-GND-loss in ON
condition are stored into an internal “fail” register. The output is then shut off. The register must be reset with a
low signal at the input. A “l(fā)ow signal” means that the input is low for a time longer than T
D
or T
DReg
for the re-
ulated channel, otherwise it is interpreted as a PWM input signal and the register is left in set mode.
Signal-GND-loss and VS-loss are detected in the active on mode, but they do not set the fail register. This type
of error is only delayed with the standard timer
t
lf
function.
Open load is detected for all four channels in on- and off-state.
Open load in off condition detects the voltage on the output pin. If this voltage is below 0.33 * VS the error reg-
ister is set and delayed with T
D
. A sink current stage pull the output down to ground, with EN high. With EN low
the output is floating in case of openload and the detection is not assured. In the ON state the load current is
monitored by the non-regulated channels. If it drops below the specified threshold value I
QU
an open load is
detected and the error register is set and delayed with T
D
. A regulated channel detects the open load in the on
state with the current regulator error detection. If the output PWM reaches 90% for a time longer than t
RE
than
an error occurs. This could happen when no load is connected, the resistivity of the load is too high or the supply
voltage too low. The same error is shown if the regulator is not able to reduce the current in the load in the time
t
RE
, so the output PWM falls below 10%.
A clock failure (clock loss) is detected when the frequency becomes lower than
f
CLK,min
. All status outputs are
OFF State
Filter time
Reset done by
t
sf
EN & IN = “LOW”
for
T
D
or
T
Dreg
timer
T
D
Open load
(under voltage detection)
Open load
(under current detection)
Overtemperature
X
t
lf
X
t
sf
timer
T
D
X
t
sf
EN & IN = “LOW”
for
T
D
or
T
Dreg
in on: EN & IN = “LOW”
for
T
D
or
T
Dreg
in off: timer
T
D
timer
T
D
timer
T
D
in on: EN & IN = “LOW”
for
T
D
or
T
Dreg
in off: timer
T
D
in on: EN & IN = “LOW”
for
T
D
or
T
Dreg
in off: timer
T
D
Power-GND-loss
X
X
t
lf
Signal-GND-loss
Supply-VS-loss
Clock control
X
X
X
X
X
X
t
lf
t
lf
no
Output voltage clamp active
X
(regulated
channels)
no
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