
19/38
L6711
Offset automatically given by the DAC selection or by VID5 when VID_SEL=SGND differs from the offset
implemented through the OFFSET pin: the built-in feature is trimmed in production and assures ±0.5%
error (±0.6% for the Hammer DAC) over load and line variations while implementing the same offset
through the OFFSET pin causes additional errors to be considered in the total output voltage precision.
When the Integrated Thermal Sensor is enabled (see Figure 12 and following section), the pin programs,
in the same way as before, a negative offset. This is to compensate the positive native offset introduced
by the ITS. The effect of the programmed offset on the output voltage results (I
OFFSET
is now added to I
FB
and no more subtracted as before):
Offset resistor is designed to compensate the ITS native offset as described in the following section.
The Offset function can be disabled by shorting the pin to SGND.
Figure 12. Voltage Positioning with Integrated Thermal Sensor
8.3
Current sense elements have non-negligible temperature variations: considering either inductor or LS
mosfet sense, the sensing elements modify proportionally to varying temperature. As a consequence, the
sensed current is subjected to a measurement error that causes the regulated voltage to vary accordingly.
To recover from this temperature related error, a temperature compensation circuit is integrated into the
controller: the internal temperature is sensed and the droop current is corrected (according to a scaling
external resistor R
TC
) in order to keep constant the regulated voltage.
The ITS circuit subtracts from the I
FB
current a current proportional to the sensed temperature as follow
(see Figure 12, Only the I
DROOP
and I
TC
contributes to I
FB
have been considered):
INTEGRATED THERMAL SENSOR
where
where A and B are positive constants depending on the value of the external resistor R
TC
(see Figure 13),
T
J
is the device junction temperature and T
MOS
is the mosfet (or the used sensing element) temperature.
The resistor R
TC
can be designed in order to zero the temperature influence on the output voltage at a
fixed current as follow:
R
OFFSET
V
OS
------------------
R
FB
=
V
OUT
VID
R
FB
I
OFFSET
–
VID
R
FB
R
OFFSET
-------------------------
–
VID
V
OS
–
=
=
=
1.240V
I
O
I
T
1:1
V
TC
=A+B·(T
J
-25)
R
TC
R
OFFSET
OFFSET
TC
1:1
I
DROOP
VID
FB
COMP
I
FB
VSEN
64k
FBR
FBG
6
64k
6
R
F
C
F
R
FB
(Remote Sense)
I
OFFSET
I
T
V
OUT
T,I
OUT
(
)
VID
R
FB
R
T
Rg
R
TC
)
-------------------------------------------
I
OUT
I
TC
T
J
(
)
–
–
=
I
TC
T
J
(
)
----------
A
B
T
J
25
–
(
)
+
[
]
=