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L6711
14/38
Figure 6. Current Reading Connections selectable through CS_SEL pin.
5.1
Leaving CS_SEL pin OPEN, the current flowing trough each phase is read using the voltage drop across
the low side mosfets R
dsON
or across a sense resistor in its series and it is internally converted into a cur-
rent. The transconductance ratio is issued by the external resistor Rg placed outside the chip between
CSx- and CSx+ pins toward the reading points (see Figure 7 right). The proprietary current sense circuit
tracks the current information for a time T
TRACK
= T
SW
/3 (T
SW
= 1/F
SW
) centered in the middle of the low-
side mosfet conduction time (OFF Time, see Figure 7 left) and holds the tracked information during the
rest of the period.
This device sources a constant 50
μ
A current from the CSx+ pin: the current reading circuitry uses this pin
as a reference and the reaction keeps the CSx- pin to this voltage during the reading time (an internal
clamp keeps CSx+ and CSx- at the same voltage sinking from the CSx- pin the necessary current during
the hold time; this is needed when LS mosfet R
dsON
sense is implemented to avoid absolute maximum
rating overcome on CSx- pin). The current that flows from the CSx- pin is then given by the following equa-
tion (See Figure 7 - right):
LOW SIDE Current Reading
where
R
dsON
is the on resistance of the low side mosfet and Rg is the transconductance resistor used between
CSx- and CSx+ pins toward the reading points; I
PHASEx
is the current carried by the relative phase and
I
INFOx
is the current information signal reproduced internally.
50
μ
A offset allows negative current reading, enabling the device to check for dangerous returning current
between the phases assuring the complete current equalization. From the current information of each
phase, information about the total current delivered (I
DROOP
= I
INFO1
+ I
INFO2
+ I
INFO3
) and the average
current for each phase (I
AVG
= (I
INFO1
+ I
INFO2
+ I
INFO3
)/3 ) is taken. I
INFOX
is then compared to I
AVG
to give
the correction to the PWMx output in order to equalize the current carried by the three phases.
Figure 7. Current reading across LS mosfet: timing (left) and circuit (right) for each phase.
CSx-
CSx+
LGATEx
Rg
Rg
I
PHASE
CS_SEL
L
R
L
R
g(RC)
C
g
Rg
CSx+
CSx-
PHASEx
OUT
I
PHASE
CS_SEL
R
g(a)
LS Mosfet Current Sense
Inductor Current Sense
I
CSx-
50
μ
A
R
R
g
-----------------
I
PHASEx
+
50
μ
A
I
INFOx
+
=
=
I
INFOx
R
R
g
-----------------
I
PHASEx
=
I
PHASEx
I
LSx
I
INFOx
T
TRACK
T
SW
CSx+
CSx-
LGATEx
I
PHASEx
50
μ
A
I
CSx-
Rg
Rg