參數(shù)資料
型號(hào)： KSZ8863FLL-EVAL
廠商： Micrel Inc
文件頁(yè)數(shù)： 51/106頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR KSZ8863FLL
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，以太網(wǎng) PHY
嵌入式： 否
已用 IC / 零件： KSZ8863FLL
已供物品： 板
相關(guān)產(chǎn)品： 576-3750-ND - IC ETHERNET SWITCH 3PORT 48-LQFP
576-3576-ND - IC ETHERNET SW 3PORT 48-LQFP
其它名稱： 576-3866
PIC16C72 Series
DS39016A-page 48
Preliminary
1998 Microchip Technology Inc.
8.4.1.1
ADDRESSING
Once the SSP module has been enabled, it waits for a
START condition to occur. Following the START condi-
tion, the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
a)
The SSPSR register value is loaded into the
SSPBUF register.
b)
The buffer full bit, BF is set.
c)
An ACK pulse is generated.
d)
SSP interrupt ag bit, SSPIF (PIR1<3>) is set
(interrupt is generated if enabled) - on the falling
edge of the ninth SCL pulse.
In 10-bit address mode, two address bytes need to be
received by the slave. The ve Most Signicant bits
(MSbs) of the rst address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a write
so the slave device will receive the second address
byte. For a 10-bit address the rst byte would equal
‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs
of the address. The sequence of events for 10-bit
address is as follows, with steps 7- 9 for slave-transmit-
ter:
1.
Receive rst (high) byte of Address (bits SSPIF,
BF, and bit UA (SSPSTAT<1>) are set).
2.
Update the SSPADD register with second (low)
byte of Address (clears bit UA and releases the
SCL line).
3.
Read the SSPBUF register (clears bit BF) and
clear ag bit SSPIF.
4.
Receive second (low) byte of Address (bits
SSPIF, BF, and UA are set).
5.
Update the SSPADD register with the rst (high)
byte of Address, if match releases SCL line, this
will clear bit UA.
6.
Read the SSPBUF register (clears bit BF) and
clear ag bit SSPIF.
7.
Receive repeated START condition.
8.
Receive rst (high) byte of Address (bits SSPIF
and BF are set).
9.
Read the SSPBUF register (clears bit BF) and
clear ag bit SSPIF.
TABLE 8-3
DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Transfer is Received
SSPSR
→ SSPBUF
Generate ACK
Pulse
Set bit SSPIF
(SSP Interrupt occurs
if enabled)
BF
SSPOV
0
Yes
1
0
No
Yes
1
No
Yes
0
1
No
Yes
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