參數(shù)資料
型號(hào)： KSZ8863FLL-EVAL
廠商： Micrel Inc
文件頁(yè)數(shù)： 106/106頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR KSZ8863FLL
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，以太網(wǎng) PHY
嵌入式： 否
已用 IC / 零件： KSZ8863FLL
已供物品： 板
相關(guān)產(chǎn)品： 576-3750-ND - IC ETHERNET SWITCH 3PORT 48-LQFP
576-3576-ND - IC ETHERNET SW 3PORT 48-LQFP
其它名稱(chēng)： 576-3866
2006 Microchip Technology Inc.
DS39564C-page 97
PIC18FXX2
9.5
PORTE, TRISE and LATE
Registers
This section is only applicable to the PIC18F4X2
devices.
PORTE is a 3-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISE. Setting a
TRISE bit (= 1) will make the corresponding PORTE pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISE bit (= 0) will
make the corresponding PORTE pin an output (i.e., put
the contents of the output latch on the selected pin).
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register reads and writes the latched output value for
PORTE.
PORTE has three pins (RE0/RD/AN5, RE1/WR/AN6
and RE2/CS/AN7) which are individually configurable
as inputs or outputs. These pins have Schmitt Trigger
input buffers.
Register 9-1 shows the TRISE register, which also
controls the parallel slave port operation.
PORTE pins are multiplexed with analog inputs. When
selected as an analog input, these pins will read as '0's.
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
EXAMPLE 9-5:
INITIALIZING PORTE
FIGURE 9-9:
PORTE BLOCK DIAGRAM
IN I/O PORT MODE
Note:
On a Power-on Reset, these pins are
configured as analog inputs.
CLRF
PORTE
; Initialize PORTE by
; clearing output
; data latches
CLRF
LATE
; Alternate method
; to clear output
; data latches
MOVLW
0x07
; Configure A/D
MOVWF
ADCON1
; for digital inputs
MOVLW
0x05
; Value used to
; initialize data
; direction
MOVWF
TRISE
; Set RE<0> as inputs
; RE<1> as outputs
; RE<2> as inputs
Data
Bus
WR LATE
WR TRISE
RD PORTE
Data Latch
TRIS Latch
RD TRISE
Schmitt
Trigger
Input
Buffer
Q
D
CK
Q
D
CK
EN
QD
EN
I/O pin(1)
RD LATE
or
PORTE
To Analog Converter
Note 1:
I/O pins have diode protection to VDD and VSS.
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