參數(shù)資料
型號： KSZ8862-16MQL
廠商： Micrel Inc
文件頁數(shù)： 95/125頁
文件大小： 0K
描述： IC SWITCH 10/100 16BIT 128-PQFP
標(biāo)準(zhǔn)包裝： 66
系列： KSZ8862
控制器類型： 以太網(wǎng)開關(guān)控制器
接口： PCI
安裝類型： 表面貼裝
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-PQFP（14x20）
包裝： 托盤
配用： 576-1638-ND - BOARD EVALUATION KSZ8862-10FL
576-1637-ND - BOARD EVALUATION KSZ8862-100FX
其它名稱： 576-1564
Micrel, Inc.
KSZ8862-16/32MQL
April 2007
71
M9999-040407-3.0
Bit
Default
R/W
Description
1
0
RW
Legal Maximum Packet Size Check Enable
0 = accepts packet sizes up to 1536 bytes (inclusive).
1 = 1522 bytes for tagged packets, 1518 bytes for untagged packets. Any packets larger than the
specified value are dropped.
0
1
RW
Priority Buffer Reserve
1 = each port is pre-allocated 48 buffers, used exclusively for high priority (q3, q2, and q1) packets.
Effective only when the multiple queue feature is turned on.
0 = each port is pre-allocated 48 buffers used for all priority packets (q3, q2,q1, and q0).
Bank 32 Switch Global Control Register 3 (0x06): SGCR3
This register contains the global control for the switch function.
Bit
Default
R/W
Description
15-8
0x63
RW
Broadcast Storm Protection Rate Bit [7:0]
These bits, along with SGCR3[2:0], determine how many 64-byte blocks of packet data are allowed
on an input port in a preset period. The period is 67ms for 100BT or 670ms for 10BT. The default is
1%.
7
0
RW
Reserved
6
0
RW
Switch Host Half-Duplex Mode
1 = enable host port interface half-duplex mode.
0 = enable host port interface full-duplex mode.
5
0
RW
Switch Flow Control Enable
1 = enable full-duplex flow control on Switch Host port.
0 = disable full-duplex flow control on Switch Host port.
4
0
RW
Reserved
3
0
RW
Null VID Replacement
1 = replaces NULL VID with port VID(12 bits).
0 = no replacement for NULL VID.
2-0
0x0
RW
Broadcast Storm Protection Rate Bit [10:8]
These bits, along with SGCR3[15:8] determine how many 64-byte blocks of packet data are allowed
on an input port in a preset period. The period is 67ms for 100BT or 670ms for 10BT. The default is
1%.
Rate: 148,800 frames/sec * 67 ms/interval * 1% = 99 frames/interval (approx.) = 0x63.
Bank 32 Switch Global Control Register 4 (0x08): SGCR4
This register contains the global control for the switch function.
Bit
Default
R/W
Description
15-0
0x2400
RW
Reserved
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