參數(shù)資料
型號: KSZ8851-16MLLJ
廠商: Micrel Inc
文件頁數(shù): 27/90頁
文件大小: 0K
描述: IC CTLR MAC 1PORT NON-PCI 48LQFP
標(biāo)準(zhǔn)包裝: 250
控制器類型: 以太網(wǎng)控制器,MAC/PHY
接口: 總線
電源電壓: 1.8V,2.5V,3.3V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 托盤
其它名稱: 576-3629
KSZ8851-16MLLJ-ND
Micrel, Inc.
KSZ8851-16MLLJ
March 2010
33
M9999-030210-1.0
Receive Queue (RXQ) Frame Format
The frame format for the receive queue is shown in Table 9. The first word contains the status information for the frame
received. The second word is the total number of bytes of the RX frame. Following that is the packet data area. The
packet data area holds the frame itself. It includes the CRC checksum.
Packet Memory
Address Offset
Bit 15
Bit 0
2
nd Byte
1
st Byte
0
Status Word
(High byte and low byte need to swap in Big-Endian
mode. Also see description in RXFHSR register)
2
Byte Count
(High byte and low byte need to swap in Big-Endian
mode. Also see description in RXFHBCR register)
4 - up
Receive Packet Data
(maximum size is 2000)
Table 9. Frame Format for Receive Queue
Frame Receiving Path Operation in RXQ
This section describes the typical register settings for receiving packets from KSZ8851-16MLLJ to host processor with
generic bus interface. User can use the default value for most of the receive registers. The following Table 10 describes
all registers which need to be set and used for receiving single or multiple frames.
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