參數(shù)資料
型號(hào): KSZ8851-16MLLJ
廠商: Micrel Inc
文件頁(yè)數(shù): 20/90頁(yè)
文件大?。?/td> 0K
描述: IC CTLR MAC 1PORT NON-PCI 48LQFP
標(biāo)準(zhǔn)包裝: 250
控制器類型: 以太網(wǎng)控制器,MAC/PHY
接口: 總線
電源電壓: 1.8V,2.5V,3.3V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 托盤
其它名稱: 576-3629
KSZ8851-16MLLJ-ND
Micrel, Inc.
KSZ8851-16MLLJ
March 2010
27
M9999-030210-1.0
Little and Big Endian Support
The KSZ8851-16MLLJ supports either Little- or Big-Endian microprocessor. The external strap pin 10 (EESK) is used to
select between two modes. The KSZ8851-16MLLJ operates in Little Endian when this pin is pulled-down or in Big Endian
when this pin is pulled-up.
When this pin 10 is no connect or tied to GND, the bit 11 (Endian mode selection) in RXFDPR register can be used to
program either Little (bit11=0) Endian mode or Big (bit11=1) Endian mode.
Asynchronous Interface
For asynchronous transfers, the asynchronous interface uses RDN (read) and WRN (write) signal strobes for data latching. The
host utilizes the rising edge of RDN to latch read data and the KSZ8851-16MLLJ will use falling edge of WRN to latch write
data.
All asynchronous transfers are either single-data or burst-data transfers. Byte or word data bus access (transfers) is
supported. The BIU, however, provides flexible asynchronous interfacing to communicate with various applications and
architectures. No additional address latch is required. The BIU qualifies both CSN (Chip Select) pin and WRN (Write
Enable) pin to write the Address A[7:2] and BE[3:0] value (in 16-bit mode) or Address A[7:0] value (in 8-bit mode) into
KSZ8851-16MLLJ when CMD (Command type) pin is high. The BIU qualifies both CSN (Chip Select) pin and RDN (Read
Enable) or WRN (Write Enable) pin to read or write the SD[15:0] data value from or to KSZ8851-16MLLJ when CMD
(Command type) pin is low.
In order for software to read back the previous CMD register write value when CMD is “1”, the BIU qualifies both CSN
(Chip Select) pin and RDN (Read Enable) pin to read the Address A[7:2] and BE[3:0] value (in 16-bit mode) or Address
A[7:0] value (in 8-bit mode) back from KSZ8851-16MLLJ when CMD (Command type) pin is high.
BIU Summation
Figure 6 shows the connection for different data bus sizes. Also refer to reference schematics in hardware design
package.
All of control and status registers in the KSZ8851-16MLLJ are accessed indirectly depending on CMD (Command type)
pin. The command sequence to access the specified control or status register is to write the register’s address (when
CMD=1) then read or write this register data (when CMD=0). If both RDN and WRN signals in the system are only used
for KSZ8851-16MLLJ, the CSN pin can be forced to active low to simplify the system design. The CMD pin can be
connected to host address line HA0 for 8-bit bus mode or HA1 for 16-bit bus mode.
Figure 6. KSZ8851-16MLLJ 8-Bit and 16-Bit Data Bus Connections
-
A2
A3
A4
A5
A6
A7
-
BE0
BE1
BE2
BE3
CMD=1
“High”
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
CMD=0
“Low”
16-Bit Bus Mode
Pin 1 (P1LED1) = NC or
Pull Up during RESET
A0
A1
A2
A3
A4
A5
A6
A7
GND
D0
D1
D2
D3
D4
D5
D6
D7
GND
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
CMD=1
“High”
CMD=0
“Low”
Shared
Data Bus
8-Bit Bus Mode
Pin 1 (P1LED1) = 1K Pull
Down during RESET
-
A2
A3
A4
A5
A6
A7
-
BE0
BE1
BE2
BE3
CMD=1
“High”
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
CMD=0
“Low”
16-Bit Bus Mode
Pin 1 (P1LED1) = NC or
Pull Up during RESET
A0
A1
A2
A3
A4
A5
A6
A7
GND
D0
D1
D2
D3
D4
D5
D6
D7
GND
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
CMD=1
“High”
CMD=0
“Low”
Shared
Data Bus
8-Bit Bus Mode
Pin 1 (P1LED1) = 1K Pull
Down during RESET
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