參數(shù)資料
型號: KSZ8841-PMQL-EVAL
廠商: Micrel Inc
文件頁數(shù): 39/74頁
文件大小: 0K
描述: BOARD EVALUATION KSZ8841-PMQL
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,以太網(wǎng)控制器(PHY 和 MAC)
嵌入式:
已用 IC / 零件: KSZ8841-PMQL
主要屬性: 1 個端口,100BASE-TX/10BASE-T
次要屬性: PCI 接口,LinkMD 線纜診斷
已供物品:
產(chǎn)品目錄頁面: 1114 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: 576-2118-ND - IC MAC CTRLR 32BIT PCI 128-PQFP
576-2117-ND - IC MAC CTRLR 32BIT 128-PQFP
其它名稱: 576-1633
Micrel, Inc.
KSZ8841-PMQL
October 2007
44
M9999-100407-1.5
These three registers value for MAC address 01:23:45:67:89:AB will be held as below:
MARL[15:0] = 0x89AB
MARM[15:0] = 0x4567
MARH[15:0] = 0x0123
The following table shows the register bit fields for low word of MAC address.
Bit
Default
R/W
Description
15-0
-
RW
MARL MAC Address Low
The least significant word of the MAC address
MAC Address Register Middle (0x0202): MARM
The following table shows the register bit fields for middle word of MAC address.
Bit
Default
R/W
Description
15-0
-
RW
MARM MAC Address Middle
The middle word of the MAC address
MAC Address Register High (0x0204): MARH
The following table shows the register bit fields for high word of MAC address.
Bit
Default
R/W
Description
15-0
-
RW
MARH MAC Address High
The Most significant word of the MAC address
On-Chip Bus Control Register (Offset 0x0210): OBCR
This register controls the on-chip bus speed for the KSZ8841-PMQL operations. It’s used for power management when
the external host CPU is running a slow frequency. The default of the on-chip bus speed is 25MHz. When the external
host CPU is running at a higher clock rate, it’s recommended the on-chip bus is adjusted accordingly for the best
performance.
Bit
Default
R/W
Description
15-2
-
RO
Reserved
1-0
0x3
RW
OBSC On-Chip Bus Speed Control
00: 125 MHz
01: 62.5 MHz
10: 41.66 MHz
11: 25 MHz
EEPROM Control Register (Offset 0x0212): EEPCR
KSZ8841-PMQL supports both with and without EEPROM system design. To support external EEPROM, tie the
EEPROM Enable (EEEN) pin to high; otherwise, tie it to Low (or no connect). Also, KSZ8841-PMQL allows software to
access (read and write) EEPROM directly. That is, the EEPROM access timing can be fully controlled by software if
EEPROM Software Access bit is set.
Bit
Default
R/W
Description
15-5
0
RO
Reserved
4
0
RW
EESA EEPROM Software Access
1 = Enable software to access EEPROM through bit 14 to bit 11.
0 = Disable software to access EEPROM.
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