參數(shù)資料
型號(hào)： KSZ8841-PMQL-EVAL
廠商： Micrel Inc
文件頁(yè)數(shù)： 22/74頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION KSZ8841-PMQL
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，以太網(wǎng)控制器（PHY 和 MAC）
嵌入式： 否
已用 IC / 零件： KSZ8841-PMQL
主要屬性： 1 個(gè)端口，100BASE-TX/10BASE-T
次要屬性： PCI 接口，LinkMD 線纜診斷
已供物品： 板
產(chǎn)品目錄頁(yè)面： 1114 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： 576-2118-ND - IC MAC CTRLR 32BIT PCI 128-PQFP
576-2117-ND - IC MAC CTRLR 32BIT 128-PQFP
其它名稱： 576-1633
Micrel, Inc.
KSZ8841-PMQL
October 2007
29
M9999-100407-1.5
Configuration ID Register (CFID Offset 00H)
The CFID register identifies the KSZ8841-PMQL. The following table shows the CFID register bit fields.
Bit
Default
Description
31 - 16
0x8841
Device ID
15 - 0
0x16C6
Vendor ID
Specifies the manufacturer of the KSZ8841-PMQL.
The following table shows the access rules of the register.
Command and Status Configuration Register (CFCS Offset 04H)
The CFCS register is divided into two sections: a command register (CFCS[15:0]) and a status register (CFCS[31:16]).
The command register provides control of the KSZ8841-PMQL’s ability to generate and respond to PCI cycles. When 0
is written to this register, the KSZ8841-PMQL logically disconnects from the PCI bus for all accesses except
configuration accesses.
The status register records status information for the PCI bus-related events. The CFCS status bits are not cleared
when they are read. Writing 1 to these bits clears them; writing 0 has no effect.
The following table describes the CFCS register bit fields.
Bit
Type
Default
Description
31
Status
0
Detected Parity Error
When set, indicates that the KSZ8841-PMQL detected a parity
error, even if parity error handling is disabled in parity error
response (CFCS[6]).
30
Status
0
Signal System Error
When set, indicates that the KSZ8841-PMQL asserted the system
error SERR_N pin.
29
Status
0
Received Master Abort
When set, indicates that the KSZ8841-PMQL terminated a master
transaction with master abort.
28
Status
0
Received Target Abort
When set, indicates that the KSZ8841-PMQL master transaction
was terminated due to a target abort.
27
Status
0
Target Abort
This bit is set by KSZ8841-PMQL whenever it terminates with a
Target Abort. The CSR registers are all 32-bit Little Endian format.
For PCI register Read cycles, the KSZ8841-PMQL allows any
different combination of CBEN. For PCI register bus cycles, only
byte, word (16-bit), or Dword (32-bit) accesses are allowed. Any
other combination is illegal and is target aborted.
26 - 25
Status
01
Device Select Timing
Indicates the timing of the assertion of device select(DEVSEL_N).
These bits are fixed at 01, which indicates a medium assertion of
DEVSEL_N.
Category
Description
Value after hardware reset
0x884116C6
Write access rules
Write has no effect on the KSZ8841-PMQL.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
KSZ8841-PMQLI 功能描述:以太網(wǎng) IC Single Ethernet Port + 32-bit/33MHz PCI interface, Ind Temp (Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
KSZ8842 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2-Port Ethernet Switch with PCI Interface
KSZ8842-16 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2-Port Ethernet Switch with Non-PCI Interface
KSZ8842-16_08 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2-Port Ethernet Switch with Non-PCI Interface
KSZ8842-16_1 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2-Port Ethernet Switch with Non-PCI Interface
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