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參數資料
| 型號： | KSZ8841-PMQL-EVAL |
| 廠商： | Micrel Inc |
| 文件頁數： | 33/74頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION KSZ8841-PMQL |
| 標準包裝： | 1 |
| 主要目的： | 接口，以太網控制器（PHY 和 MAC） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | KSZ8841-PMQL |
| 主要屬性： | 1 個端口，100BASE-TX/10BASE-T |
| 次要屬性： | PCI 接口，LinkMD 線纜診斷 |
| 已供物品： | 板 |
| 產品目錄頁面： | 1114 (CN2011-ZH PDF) |
| 相關產品： | 576-2118-ND - IC MAC CTRLR 32BIT PCI 128-PQFP 576-2117-ND - IC MAC CTRLR 32BIT 128-PQFP |
| 其它名稱： | 576-1633 |
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Micrel, Inc.
KSZ8841-PMQL
October 2007
39
M9999-100407-1.5
MAC DMA Receive Start Command Register (MDRSC Offset 0x000C)
This register is written by the CPU when there are frame data in receive buffer to be processed.
The following table shows the register bit fields.
Bit
Default \
Read/
Write
Description
31 - 0
0x00000000
WO
WRSC Receive Start Command
When written with any value, the Receive DMA checks for descriptors
to be acquired. If no descriptor is available, the receive process returns
to suspended state and wait for the next receive restart command. If
descriptors are available, the receive process resumes. This bit is self-
clearing.
Transmit Descriptor List Base Address Register (TDLB Offset 0x0010)
This register is used for Transmit descriptor list base address register. The register is used to point to the start of the
appropriate descriptor list. Writing to this register is permitted only when its respective process is in the stopped state.
When stopped, the register must be written before the respective START command is given.
Note: The descriptor lists must be Word (32-bit) aligned. The KSZ8841-PMQL behavior is unpredictable when the lists are not word-
aligned.
The following table shows the register bit fields.
Bit
Default
Read/
Write
Description
31 - 0
0x00000000
RW
WSTL Start of Transmit List
Note: Write can only occur when the transmit process stopped.
Receive Descriptor List Base Address Register (RDLB Offset 0x0014)
This register is used for Receive descriptor list base address register. The register is used to point to the start of the
appropriate descriptor list. Writing to this register is permitted only when its respective process is in the stopped state.
When stopped, the register must be written before the respective START command is given.
Note: The descriptor lists must be Word (32-bit) aligned. The KSZ8841-PMQL behavior is unpredictable when the lists are not word-
aligned.
The following table shows the register bit fields.
Bit
Default
Read/
Write
Description
31 - 0
0x00000000
RW
WSRL Start of Receive List
Note: Write can only occur when the transmit process stopped.
MAC Multicast Table 0 Register (MTR0 Offset 0x0020)
The 64 bit multicast table is used for group address filtering. The value is defined as the six most significant bits of the
CRC of the DA. The two most significant bits select the register to be used, while the other determines the bit within the
register.
Bit
Default
Read/
Write
Description
31-0
0x00000000
RW
MTR0 Multicast Table 0
When appropriate bit is set, the packet received with DA matches the
CRC hashing function is received without being filtered.
Note: when receive all (RXRA) or receive multicast (RXRM) bit is set in
the RXCR then all multicast addresses are received regardless of the
multicast table value.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| KSZ8841-PMQLI | 功能描述:以太網 IC Single Ethernet Port + 32-bit/33MHz PCI interface, Ind Temp (Lead Free) RoHS:否 制造商:Micrel 產品:Ethernet Switches 收發(fā)器數量:2 數據速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8842 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2-Port Ethernet Switch with PCI Interface |
| KSZ8842-16 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2-Port Ethernet Switch with Non-PCI Interface |
| KSZ8842-16_08 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2-Port Ethernet Switch with Non-PCI Interface |
| KSZ8842-16_1 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2-Port Ethernet Switch with Non-PCI Interface |
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