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參數(shù)資料
| 型號： | KSZ8841-PMQL-EVAL |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 36/74頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION KSZ8841-PMQL |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 接口，以太網(wǎng)控制器（PHY 和 MAC） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | KSZ8841-PMQL |
| 主要屬性： | 1 個(gè)端口，100BASE-TX/10BASE-T |
| 次要屬性： | PCI 接口，LinkMD 線纜診斷 |
| 已供物品： | 板 |
| 產(chǎn)品目錄頁面： | 1114 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | 576-2118-ND - IC MAC CTRLR 32BIT PCI 128-PQFP 576-2117-ND - IC MAC CTRLR 32BIT 128-PQFP |
| 其它名稱： | 576-1633 |
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Micrel, Inc.
KSZ8841-PMQL
October 2007
41
M9999-100407-1.5
Bit
Default
Read/
Write
Description
25
0
RW
DMRPSIE DMA MAC Receive Process Stopped Interrupt Enable
When this bit is set, the DMA MAC Receive Process Stopped Interrupt
is enabled.
When this bit is reset, the DMA MAC Receive Process Stopped
Interrupt is disabled.
24 - 0
-
RO
Reserved
Interrupt Status Register (INTST Offset 0x002C)
This register contains all the status bits for the ARM CPU. When corresponding enable bit is set, it cause the CPU to be
interrupted. This register is usually read by the driver during interrupt service routine or polling. The register bits are not
cleared when read. Each field can be masked.
The following table shows the register bit fields.
Bit
Default
Read/
Write
Description
31
0
RW
DMLCS DMA MAC Link Changed Status
When this bit is set, it indicates that the DMA MAC link status has
changed from link up to link down or from link down to link up.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
30
0
RW
DMTS DMA MAC Transmit Status
When this bit is set, it indicates that the DMA MAC has transmitted at
least a frame on the DMA port and the MAC is ready for new frames
from the host.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
29
0
RW
DMRS DMA MAC Receive Status
When this bit is set, it indicates that the DMA MAC has received a
frame from the DMA port and it is ready for the host to process
This edge-triggered interrupt status is cleared by writing 1 to this bit.
28
0
RW
DMTBUS DMA MAC Transmit Buffer Unavailable Status
When this bit is set, it indicates that the next descriptor on the transmit
list is owned by the host and cannot be acquired by the KSZ8841-
PMQL. The transmission process is suspended. To resume processing
transmit descriptors, the host should change the ownership bit of the
descriptor and then issue a transmit start command.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
27
0
RW
DMRBUS DMA MAC Receive Buffer Unavailable Status
When this bit is set, it indicates that the descriptor list is owned by the
host and cannot be acquired by the KSZ8841-PMQL. The receiving
process is suspended. To resume processing receive descriptors, the
host should change the ownership of the descriptor and may issue a
receive start command. If no receive start command is issued, the
receiving process resumes when the next recognized incoming frame is
received. After the first assertion, this bit is not asserted for any
subsequent not owned receive descriptors fetches. This bit is asserted
only when the previous receive descriptor was owned by the KSZ8841-
PMQL.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
26
0
RW
DMTPSS DMA MAC Transmit Process Stopped Status
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KSZ8841-PMQLI | 功能描述:以太網(wǎng) IC Single Ethernet Port + 32-bit/33MHz PCI interface, Ind Temp (Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8842 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2-Port Ethernet Switch with PCI Interface |
| KSZ8842-16 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2-Port Ethernet Switch with Non-PCI Interface |
| KSZ8842-16_08 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2-Port Ethernet Switch with Non-PCI Interface |
| KSZ8842-16_1 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2-Port Ethernet Switch with Non-PCI Interface |
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