參數(shù)資料
型號: KSZ8695X-EVAL
廠商: Micrel Inc
文件頁數(shù): 8/39頁
文件大?。?/td> 0K
描述: KIT EVAL KSZ8695X EXPERIMENT
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,以太網(wǎng) PHY
嵌入式:
已用 IC / 零件: KSZ8695X
主要屬性: 單芯片網(wǎng)關(guān)解決方案
已供物品:
相關(guān)產(chǎn)品: 576-1025-ND - IC SWITCH 10/100 5PORT 208PQFP
其它名稱: 576-1624
Micrel, Inc.
KS8695X
June 2006
16
M9999-060106
Signal Description
System Level Hardware Interfaces
Figure 2. System Level Interfaces
At the system level the KS8695X features the following interfaces:
Clock interface for crystal or external oscillator
JTAG development interface
One WAN Ethernet physical interface
Four LAN Ethernet physical interfaces
PHY LED drivers
One high-speed UART interface
Eight GPIO pins
Advanced memory interface
– Programmable synchronous bus rate
– Programmable asynchronous interface timing
– Independently programmable data bus width for static and synchronous memory
– Glueless connection to SDRAM
– Glueless connection to ash memory or ROM
Factory test
Power and ground
Configuration Pins
The following pins are sampled as input during reset.
Configuration
Pin Name
Pin #
Setting
Bank0 Flash Data Width
B0SIZE[1:0]
118, 119
‘00’= reserved
‘01’ = byte wide
‘10’ = half word wide (16 bits)
‘11’ = word wide (32 bits)
WRSTO Polarity
EROEN/WRSTPLS
85
‘0’ = active high
‘1’ = active low
CPU Clock Select
URTSN/CPUCLKSEL
96
‘0’ = normal mode (PLL)
'1’ = bypass internal PLL
Table 1. Configuration Pins
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