參數(shù)資料
型號(hào): KSZ8695X-EVAL
廠商: Micrel Inc
文件頁數(shù): 1/39頁
文件大?。?/td> 0K
描述: KIT EVAL KSZ8695X EXPERIMENT
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,以太網(wǎng) PHY
嵌入式:
已用 IC / 零件: KSZ8695X
主要屬性: 單芯片網(wǎng)關(guān)解決方案
已供物品:
相關(guān)產(chǎn)品: 576-1025-ND - IC SWITCH 10/100 5PORT 208PQFP
其它名稱: 576-1624
KS8695X
Integrated Multi-Port High-Performance
Gateway Solution
Rev. 1.03
XceleRouter is a trademark of Micrel, Inc. AMD is a registered trademark of Advanced Micro Devices, Inc. ARM is a trademark of Advanced RISC Machines Ltd.
Intel is a registered trademark of Intel Corporation. WinCE is a registered trademark of Microsoft Corporation.
Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (
408) 944-0800 fax + 1 (408) 474-1000 http://www.micrel.com
June 2006
M9999-060106
General Description
The CENTAUR KS8695X, Multi-Port Gateway-on-a-Chip,
delivers a new level of networking integration and
performance
for
accelerating
broadband
gateway
development. Key components integrated in the KS8695X
include:
Integrated Layer 2 managed switch with five Fast
Ethernet transceivers and patented mixed-signal low-
power technology, five media access control (MAC)
units, a high-speed non-blocking switch fabric, a
dedicated address look-up engine, an on-chip frame
buffer memory, and LED controls. One port is partitioned
for WAN interface with the other four ports for LAN
access.
A 166MHz ARM (ARM992T) processor with memory
management unit (MMU) and 8KB I-cache and 8KB D-
cache.
XceleRouter technology for the WAN and LAN
interfaces.
Shared programmable 8/16/32-bit data bus and 22-bit
address bus with up to 64MB total memory space for
SDRAM, ROM, Flash, SRAM, and all peripheral devices.
Other peripheral support logic including GPIO, a
watchdog timer, an interrupt controller, and a JTAG
debugging interface.
Complete hardware and software reference designs are
available.
The KS8695X represents a new level of total solution
optimized for broadband gateway system development
and renders speedy routing performance and connectivity
interfaces for value-added networking expansions.
Functional Diagram
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