參數(shù)資料
型號: KSZ8695X-EVAL
廠商: Micrel Inc
文件頁數(shù): 10/39頁
文件大?。?/td> 0K
描述: KIT EVAL KSZ8695X EXPERIMENT
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,以太網(wǎng) PHY
嵌入式:
已用 IC / 零件: KSZ8695X
主要屬性: 單芯片網(wǎng)關(guān)解決方案
已供物品:
相關(guān)產(chǎn)品: 576-1025-ND - IC SWITCH 10/100 5PORT 208PQFP
其它名稱: 576-1624
Micrel, Inc.
KS8695X
June 2006
18
M9999-060106
Signal Descriptions by Group
Clock and Reset Pins
Pin
Name
I/O Type
(1)
Description
150
XCLK1/
CPUCLK
I
External Clock In. This signal is used as the source clock for the transmit clock of
the internal MAC and PHY. The clock frequency should be 25MHz ±50ppm. The
XCLK1 signal is also used as the reference clock signal for the internal PLL
togenerate the 125MHz internal system clock.
CPUCLK: factory clock test input when the internal PLL is disabled (factory test
signal).
151
XCLK2
I
External Clock In. Used with XCLK1 pin when another polarity of crystal is needed.
This is unused for a normal clock input.
96
URTSN/
CPUCLKSEL
O/I
Normal Mode: UART request to send. Active low output.
During reset: CPU clock select. Select CPU clock source. CPUCLKSEL=0 (normal
mode), the internal PLL clock output is used as the CPU clock source.
CPUCLKSEL=1 (factory test signal): the external clock to the CPUCLK pin is used
as the internal CPU clock source.
148
RESETN
I
KS8695X chip reset. Active low input asserted for at least 256 system clock (40ns)
cycles to reset the KS8695X. When in the reset state, all the output pins are tri-
stated and all open drain signals are floating.
83
WRSTO
O
Watchdog timer reset output. This signal is asserted for at least 200ms if RESETN
is asserted or when the internal watchdog timer expires.
85
EROEN/
WRSTPLS
O/I
Normal Mode: ROM/SRAM/FLASH and External I/O output enable. Active low.
When asserted, this signal controls the output enable port of the specified device.
During reset: Watchdog timer reset polarity setting. WRSTPLS=0, Active high;
WRSTPLS=1, Active low. No default.
JTAG Interface Pins
Pin
Name
I/O Type
(1)
Description
110
TCK
I
JTAG test clock.
111
TMS
I
JTAG test mode select.
112
TDI
I
JTAG test data in.
113
TDO
O
JTAG test data out.
114
TRSTN
I
JTAG test reset. Active low.
WAN Ethernet Physical Interface Pins
Pin
Name
I/O Type
(1)
Description
159
WANRXP
I
WAN PHY receive signal + (differential).
160
WANRXM
I
WAN PHY receive signal – (differential).
162
WANTXM
O
WAN PHY transmit signal – (differential).
163
WANTXP
O
WAN PHY transmit signal + (differential).
158
WANFXSD/
DOUT
I/O
WAN fiber signal detect. Signal detect input when the WAN port is operated in
100BASE-FX 100Mb fiber mode. DOUT:factory analog test mode.
Note
:
1. I = Input.
O = Output.
I/O = Bidirectional.
O/I = Output in normal mode; input pin during reset.
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