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參數(shù)資料
| 型號： | KSZ8695X-EVAL |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 14/39頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT EVAL KSZ8695X EXPERIMENT |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 接口，以太網(wǎng) PHY |
| 嵌入式： | 否 |
| 已用 IC / 零件： | KSZ8695X |
| 主要屬性： | 單芯片網(wǎng)關(guān)解決方案 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | 576-1025-ND - IC SWITCH 10/100 5PORT 208PQFP |
| 其它名稱： | 576-1624 |
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Micrel, Inc.
KS8695X
June 2006
21
M9999-060106
Resered Pins
Pin
Name
I/O Type
(1)
Description
84
TEST3
NC
The Reserved Pins serve as no connect in order to ensure correct operation of the
device. DO NOT connect any signal to these pins.
130
TEST4
NC
No connect.
131
TEST5
NC
No connect.
132
TEST6
NC
No connect.
133
TEST7
NC
No connect.
134
TEST8
NC
No connect.
135
TEST9
NC
No connect.
136
TEST10
NC
No connect.
139
TEST11
NC
No connect.
140
TEST12
NC
No connect.
141
TEST13
NC
No connect.
142
TEST14
NC
No connect.
143
TEST15
NC
No connect.
144
TEST16
NC
No connect.
145
TEST17
NC
No connect.
146
TEST18
NC
No connect.
147
TEST19
NC
No connect.
Advanced Memory Interface (SDRAM/ROM/FLASH/SRAM/EXTERNAL I/O)
Pin
Name
I/O Type
(1)
Description
24
SDICLK
I
SDRAM Clock In: SDRAM clock input for the SDRAM memory controller interface.
23
SDOCLK
O
System/SDRAM Clock Out: Output of the internal system clock, it is also used as
the clock signal for SDRAM interface.
205
ADDR21/BA1
O
Address Bit 21/Bank Address Input 1: Address bit 21 for asynchronous accesses.
Bank Address Input bit 1 for SDRAM accesses.
206
ADDR20/BA0
O
Address Bit 20/Bank Address Input 0: Address bit 20 for asynchronous accesses.
Bank Address Input bit 0 for SDRAM accesses.
198
199
200
201
202
203
204
207
208
3
4
5
6
7
8
9
10
13
14
15
ADDR[19]
ADDR[18]
ADDR[17]
ADDR[16]
ADDR[15]
ADDR[14]
ADDR[13]
ADDR[12]
ADDR[11]
ADDR[10]
ADDR[9]
ADDR[8]
ADDR[7]
ADDR[6]
ADDR[5]
ADDR[4]
ADDR[3]
ADDR[2]
ADDR[1]
ADDR[0]
O
Address Bus: The 22-bit address bus (including ADDR[21:20] above) covers 4M
word memory space shared by ROM/SRAM/FLASH, SDRAM, and external I/O
banks. During the SDRAM cycles, the internal address bus is used to generate RAS
and CAS addresses for the SDRAM. The number of column address bits in the
SDRAM banks can be programmed from 8 to 11 bits via the SDRAM control
registers. ADDR[12:0] are the SDRAM address, and ADDR[21:20] are the SDRAM
bank address. During other cycles, the ADDR[21:0] is the byte address of the data
transfer.
Note: The address pinout non-sequential by design. It is optimized for board level
connections to SDRAM.
For SDRAM and ROM/SRAM/Flash, connect ADDR[0] to A0 on the memory,
ADDR[1] to A1 on the memory, and so forth. Address bit mapping for 8-bit, 16-bit,
32-bit access.
For external I/O devices, the system designer must connect address lines
conventionally for 8-bit, 16-bit, and 32-bit access.
Note
:
1. I = Input.
O = Output.
NC = No connect.
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