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參數(shù)資料
| 型號(hào)： | KSZ8051MLLI TR |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 32/51頁(yè) |
| 文件大小： | 0K |
| 描述： | TXRX PHY 10/T100 3.3V MII 48LQFP |
| 特色產(chǎn)品： | KSZ8051/8031/8021 Series |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類(lèi)型： | PHY 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 1/1 |
| 規(guī)程： | MII |
| 電源電壓： | 1.8V，2.5V，3.3V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 配用： | 576-3864-ND - BOARD EVALUATION FOR KSZ8051MLL |
| 其它名稱(chēng)： | 576-3888-6 |
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MCP4017/18/19
DS22147A-page 38
2009 Microchip Technology Inc.
5.4.1
WRITE OPERATION
The write operation requires the START condition,
Control Byte, Acknowledge, Data Byte, Acknowledge
and STOP (or RESTART) condition. The Control (Slave
Address) Byte requires the R/W bit equal to a logic zero
(R/W = “0”) to generate a write sequence. The
MCP4017/18/19 is responsible for generating the
Acknowledge (A) bits.
Data is written to the MCP4017/18/19 after every byte
transfer (during the A bit). If a STOP or RESTART
condition is generated during a data transfer (before
the A bit), the data will not be written to MCP4017/18/
19.
Data bytes may be written after each Acknowledge.
The command is terminated once a Stop (P) condition
occurs. Refer to Figure 5-12 for the write sequence.
For a single byte write, the master sends a STOP or
RESTART condition after the 1st data byte is sent.
The MSb of each Data Byte is a don’t care, since the
wiper register is only 7-bits wide.
the Master Device and the MCP4017/18/19 device and
the resultant I2C bus values.
5.4.2
READ OPERATIONS
The read operation requires the START condition,
Control Byte, Acknowledge, Data Byte, the master
generating the A and STOP condition. The Control
Byte requires the R/W bit equal to a logic one (R/W =
1) to generate a read sequence. The MCP4017/18/19
will A the Slave Address Byte and A all the Data Bytes.
The I2C Master will A the Slave Address Byte and the
last Data Byte. If there are multiple Data Bytes, the I2C
Master will A all Data Bytes except the last Data Byte
(which it will A).
The MCP4017/18/19 maintains control of the SDA
signal until all data bits have been clocked out.
The command is terminated once a Stop (P) condition
occurs. Refer to Figure 5-13 for the read command
sequence. For a single read, the master sends a STOP
or RESTART condition after the 1st data byte (and A
bit) is sent from the slave.
the Master Device and the MCP4017/18/19 device and
the resultant I2C bus values.
FIGURE 5-12:
I2C Write Command Format.
STOP bit
Slave Address Byte
Data Byte
1
010
S1 1 1
0
D3
AD2 D1 D0 A
D3
xD6 D5 D4
D2 D1 D0 A
Fixed
Address
Data Byte
AD3
x D6 D5D4
D2D1 D0 A P
Read/Write bit (“0” = Write)
xD6 D5 D4
D3 D2 D1 D0
xD6 D5 D4
S = Start Condition
P = Stop Condition
A = Acknowledge
X = Don’t Care
R/W = Read/Write bit
D6, D5, D4, D3, D2, D1, D0 = Data bits
Legend
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| KSZ8051MNL | 功能描述:TXRX PHY 10/T100 3.3V MII 32-QFN RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,140 系列:AU 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):1/1 規(guī)程:CAN 電源電壓:5.3 V ~ 27 V 安裝類(lèi)型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SO 包裝:管件 其它名稱(chēng):935267940512AU5790D14AU5790D14-ND |
| KSZ8051MNL TR | 功能描述:以太網(wǎng) IC 3.3V, 10Base-T/100Base-TX Physical Layer Transceiver w/ MII Support (32-QFN) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
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| KSZ8051MNLI | 功能描述:TXRX PHY 10/T100 3.3V 32QFN RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,140 系列:AU 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):1/1 規(guī)程:CAN 電源電壓:5.3 V ~ 27 V 安裝類(lèi)型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SO 包裝:管件 其它名稱(chēng):935267940512AU5790D14AU5790D14-ND |
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