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參數(shù)資料
型號(hào)： KSZ8051MLLI TR
廠商： Micrel Inc
文件頁(yè)數(shù)： 29/51頁(yè)
文件大?。?/td> 0K
描述： TXRX PHY 10/T100 3.3V MII 48LQFP
特色產(chǎn)品： KSZ8051/8031/8021 Series
標(biāo)準(zhǔn)包裝： 1
類型： PHY 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù)： 1/1
規(guī)程： MII
電源電壓： 1.8V，2.5V，3.3V
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 標(biāo)準(zhǔn)包裝
配用： 576-3864-ND - BOARD EVALUATION FOR KSZ8051MLL
其它名稱： 576-3888-6
2009 Microchip Technology Inc.
DS22147A-page 35
MCP4017/18/19
5.2.5
STOP BIT
The Stop bit (see Figure 5-6) Indicates the end of the
I2C Data Transfer Sequence. The Stop bit is defined as
the SDA signal rising when the SCL signal is “High”.
A Stop bit resets the I2C interface of the other devices.
FIGURE 5-6:
Stop Condition Receive or
Transmit Mode.
5.2.6
CLOCK STRETCHING
“Clock Stretching” is something that the Secondary
Device can do, to allow additional time to “respond” to
the “data” that has been received.
The MCP4017/18/19 will not strech the clock signal
(SCL) since memory read accesses occur fast enough.
5.2.7
ABORTING A TRANSMISSION
If any part of the I2C transmission does not meet the
command format, it is aborted. This can be intentionally
accomplished with a START or STOP condition. This is
done so that noisy transmissions (usually an extra
START or STOP condition) are aborted before they
corrupt the device.
5.2.8
IGNORING AN I2C TRANSMISSION
AND “FALLING OFF” THE BUS
The MCP4017/18/19 expects to receive entire, valid
I2C commands and will assume any command not
defined as a valid command is due to a bus corruption
and will enter a passive high condition on the SDA
signal. All signals will be ignored until the next valid
START condition and CONTROL BYTE are received.
FIGURE 5-7:
Typical 16-bit I2C Waveform Format.
FIGURE 5-8:
I2C Data States and Bit Sequence.
SCL
SDA A / A
P
1st
SDA
SCL
S
2nd 3rd 4th 5th 6th 7th 8th
P
A/A
Bit Bit Bit Bit Bit Bit Bit Bit
1st 2nd 3rd 4th 5th 6th 7th 8th A/A
Bit Bit Bit Bit Bit Bit Bit Bit
SCL
SDA
START
Condition
STOP
Condition
Data allowed
to change
Data or
A valid
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