參數(shù)資料
型號(hào)： KP80524NY450128
英文描述： Microprocessor
中文描述： 微處理器
文件頁(yè)數(shù)： 29/81頁(yè)
文件大?。?/td> 598K
代理商： KP80524NY450128
Mobile Intel
Celeron Processor (0.18μ) in BGA2 and Micro-PGA2 Packages
Order Number#249563-001
Datasheet
29
Table 15. GTL+ Signal Groups AC Specifications
1
R
TT
=
56
internally
terminated to
V
CCT
;
V
REF
=
2
/
3
V
CCT
; load = 0 pF;
T
J
= 0°C to 100°C; V
CC
= 1.10V ±80 mV or 1.35V ±100 mV or 1.60V ±115 mV; V
CCT
= 1.50V ±115 mV
Symbol
Parameter
Min
Max
Unit
Figure
Notes
T7
GTL+ Output Valid Delay
0.2
2.7
3.4
ns
Figure 7
Note 6
Note 7
T8
GTL+ Input Setup Time
1.2
ns
Figure 8
Notes 2, 3
T9
GTL+ Input Hold Time
0.80
1.2
ns
Figure 8
Note 4, 6
Note 7
T10
RESET# Pulse Width
1.0
ms
Figure 9,
Figure 10
Note 5
NOTES:
1.
All AC timings for GTL+ signals are referenced to the BCLK rising edge at 1.25V. All GTL+ signals are
referenced at V
REF
.
RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
Specification is for a minimum 0.40V swing.
Specification is for a maximum 1.0V swing.
After V
CC
, V
CCT
, and BCLK become stable and PWRGOOD is asserted.
Applies to all core Vcc other than 1.10V
Applies only to core Vcc = 1.10V
2.
3.
4.
5.
6.
7.
Table 16. CMOS and Open-drain Signal Groups AC Specifications
1, 2
T
J
= 0°C to 100°C; V
CC
= 1.10V ±80 mV or 1.35V ±100 mV or 1.60V ±115 mV; V
CCT
= 1.50V ±115 mV
Symbol Parameter
Min Max Unit
Figure
Notes
T14
1.5V Input Pulse Width, except PWRGOOD and
LINT[1:0]
2
BCLKs Figure 7
Active and
Inactive states
T14B
LINT[1:0] Input Pulse Width
6
BCLKs Figure 7
Note 3
T15
NOTES:
1.
PWRGOOD Inactive Pulse Width
10
BCLKs Figure 10 Notes 4, 5
All AC timings for CMOS and Open-drain signals are referenced to the BCLK rising edge at 1.25V. All
CMOS and Open-drain signals are referenced at 0.75V.
Minimum output pulse width on CMOS outputs is 2 BCLKs.
This specification only applies when the APIC is enabled and the LINT1 or LINT0 signal is configured as
an edge triggered interrupt with fixed delivery, otherwise specification T14 applies.
When driven inactive, or after V
, V
and BCLK become stable. PWRGOOD must remain below V
from Table 12 until all the voltage planes meet the voltage tolerance specifications in Table 9 and BCLK
has met the BCLK AC specifications in Table 13 for at least 10 clock cycles. PWRGOOD must rise glitch-
free and monotonically to 2.5V.
If the BCLK Settling Time specification (T60) can be guaranteed at power-on reset then the PWRGOOD
Inactive Pulse Width specification (T15) is waived and BCLK may start after PWRGOOD is asserted.
PWRGOOD must still remain below V
IL25,max
until all the voltage planes meet the voltage tolerance
specifications.
2.
3.
4.
5.
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