參數(shù)資料
型號(hào)： KP80524NY450128
英文描述： Microprocessor
中文描述： 微處理器
文件頁(yè)數(shù)： 28/81頁(yè)
文件大小： 598K
代理商： KP80524NY450128
Mobile Intel
Celeron Processor (0.18μ) in BGA2 and Micro-PGA2 Packages
Datasheet
Order Number#249563-001
28
Table 15 contains the GTL+ specifications; Table 16 contains the CMOS and Open-drain signal
groups specifications; Table 17 contains timings for the reset conditions; Table 18 contains the
APIC specifications; Table 19 contains the TAP specifications; and Table 20 and Table 21 contain
the power management timing specifications.
All system bus AC specifications for the GTL+ signal group are relative to the rising edge of the
BCLK input at 1.25V. All GTL+ timings are referenced to V
REF
for both “0” and “1” logic levels
unless otherwise specified. All APIC, TAP, CMOS, and Open-drain signals except PWRGOOD
are referenced to 0.75V.
Table 13. System Bus Clock AC Specifications
1
T
J
= 0°C to 100°C; V
CC
= 1.10V ±80 mV or 1.35V ±100 mV or 1.60V ±115 mV; V
CCT
= 1.50V ±115 mV
Symbol
Parameter
Min
Typ
Max
Unit
Figure
Notes
System Bus Frequency
100
MHz
T1
BCLK Period
10
ns
Figure 6
Note 2
T2
BCLK Period Stability
±250
ps
Notes 3, 4
T3
BCLK High Time
2.70
ns
Figure 6
at >2.0V
T4
BCLK Low Time
2.45
ns
Figure 6
at <0.5V
T5
BCLK Rise Time
0.175
0.875
ns
Figure 6
(0.9V – 1.6V)
T6
BCLK Fall Time
0.175
0.875
ns
Figure 6
(1.6V – 0.9V)
NOTES:
1.
All AC timings for GTL+ and CMOS signals are referenced to the BCLK rising edge at 1.25V. All CMOS
signals are referenced at 0.75V.
The BCLK period allows a +0.5 ns tolerance for clock driver variation.
Not 100% tested. Specified by design/characterization.
Measured on the rising edge of adjacent BCLKs at 1.25V. The jitter present must be accounted for as a
component of BCLK skew between devices.
2.
3.
4.
Table 14. Valid Mobile Intel Celeron Processor Frequencies
T
J
= 0°C to 100°C; V
CC
= 1.10V ±80 mV or 1.35V ±100 mV or 1.60V ±115 mV; V
CCT
= 1.50V ±115 mV
BCLK Frequency
(MHz)
Frequency Multiplier
Core Frequency
(MHz)
Power-on Configuration
bits [27, 25:22]
100
4.0
400A
0, 0010
100
4.5
450
0, 0110
100
5.0
500
0, 0000
100
5.5
550
0, 0100
100
6.0
600
0, 1011
100
6.5
650
0, 1111
100
7.0
700
0, 1001
100
7.5
750
0, 1101
NOTE:
While other combinations of bus and core frequencies are defined, operation at frequencies other
than those listed above will not be validated by Intel and are not guaranteed. The frequency multiplier
is programmed into the processor when it is manufactured and it cannot be changed.
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